Convolutional neural network (CNN) has become a successful algorithm in the region of artificial intelligence and a strong candidate for many computer vision algorithms. But the computation ...complexity of CNN is much higher than traditional algorithms. With the help of GPU acceleration, CNN-based applications are widely deployed in servers. However, for embedded platforms, CNN-based solutions are still too complex to be applied. Various dedicated hardware designs on field-programmable gate arrays (FPGAs) have been carried out to accelerate CNNs, while few of them explore the whole design flow for both fast deployment and high power efficiency. In this paper, we investigate state-of-the-art CNN models and CNN-based applications. Requirements on memory, computation and the flexibility of the system are summarized for mapping CNN on embedded FPGAs. Based on these requirements, we propose Angel-Eye, a programmable and flexible CNN accelerator architecture, together with data quantization strategy and compilation tool. Data quantization strategy helps reduce the bit-width down to 8-bit with negligible accuracy loss. The compilation tool maps a certain CNN model efficiently onto hardware. Evaluated on Zynq XC7Z045 platform, Angel-Eye is 6× faster and 5× better in power efficiency than peer FPGA implementation on the same platform. Applications of VGG network, pedestrian detection and face alignment are used to evaluate our design on Zynq XC7Z020. NIVIDA TK1 and TX1 platforms are used for comparison. Angel-Eye achieves similar performance and delivers up to 16× better energy efficiency.
Neural networks have been widely and deeply studied in the field of computational neurodynamics. However, coupled neural networks and their brain-like chaotic dynamics have not been noticed yet. In ...this article, we focus on the coupled neural network-based brain-like initial boosting coexisting hyperchaos and its application in biomedical image encryption. We first construct a memristive-coupled neural network (MCNN) model based on two subneural networks and one multistable memristor synapse. Then we investigate its coupling strength-related dynamical behaviors, initial states-related dynamical behaviors, and initial-boosted coexisting hyperchaos using bifurcation diagrams, phase portraits, Lyapunov exponents, and attraction basins. The numerical results demonstrate that the proposed MCNN not only can generate hyperchaotic attractors with high complexity but also can boost the attractor positions by switching their initial states. This makes the MCNN more suitable for many chaos-based engineering applications. Moreover, we design a biomedical image encryption scheme to explore the application of the MCNN. Performance evaluations show that the designed cryptosystem has several advantages in the keyspace, information entropy, and key sensitivity. Finally, we develop a field-programmable gate array test platform to verify the practicability of the presented MCNN and the designed medical image cryptosystem.
Due to the natural nonlinearity and unique memory characteristics, memristors are promising candidates for the construction of multiscroll attractors having better application potential in the field ...of information encryption than the traditional double-scroll attractors. This article proposes a novel memristive multidouble-scroll Chua's system (MMDSCS) via coupling a nonideal flux-controlled memristor with multipiecewise-linear memductance function in Chua's system directly. Specially, any number of multidouble-scroll chaotic attractors can be generated through adjusting the internal parameters of the memristor conveniently and without changing the original system's nonlinearity. Moreover, the amount of double scrolls is also closely related to the strength of the memristive coupling. Another striking highlight is that infinite initial offset-boosted coexisting Chua's double-scroll attractors with the same shape are produced with the variation of the memristor initial conditions, indicating the emergence of an intriguing phenomenon of homogeneous extreme multistability. This unique property and its formation mechanism are investigated in detail using phase portraits, bifurcation diagrams, Lyapunov exponents, time series, and attraction basins. Furthermore, hardware experiments based on the field-programmable gate array are carried out to confirm the numerical simulations. Finally, an image encryption scheme is designed based on the memristor initial offset boosting dynamics from a perspective of engineering application. In comparison with the existing memristive Chua's systems, the proposed MMDSCS has many merits, such as multidouble-scroll attractors, memristor initial-controlled chaotic sequences with controllability, good robustness, and high security performance, which is more practical in applications involving information confidential communication.
A Survey and Evaluation of FPGA High-Level Synthesis Tools Nane, Razvan; Sima, Vlad-Mihai; Pilato, Christian ...
IEEE transactions on computer-aided design of integrated circuits and systems,
2016-Oct., 2016-10-00, 20161001, Letnik:
35, Številka:
10
Journal Article
Recenzirano
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High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today's system complexity. ...HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality. Additionally, HLS is particularly interesting for designing field-programmable gate array circuits, where hardware implementations can be easily refined and replaced in the target device. Recent years have seen much activity in the HLS research community, with a plethora of HLS tool offerings, from both industry and academia. All these tools may have different input languages, perform different internal optimizations, and produce results of different quality, even for the very same input description. Hence, it is challenging to compare their performance and understand which is the best for the hardware to be implemented. We present a comprehensive analysis of recent HLS tools, as well as overview the areas of active interest in the HLS research community. We also present a first-published methodology to evaluate different HLS tools. We use our methodology to compare one commercial and three academic tools on a common set of C benchmarks, aiming at performing an in-depth evaluation in terms of performance and the use of resources.
Polynomial functions have been the main barrier restricting the circuit realization and engineering application of multiwing chaotic systems (MWCSs). To eliminate this bottleneck, we construct a ...simple MWCS without polynomial functions by introducing a sinusoidal function in a Sprott C system. Theoretical analysis and numerical simulations show that the MWCS can not only generate multibutterfly attractors with an arbitrary number of butterflies, but also adjust the number of the butterflies by multiple ways including self-oscillating time, control parameters, and initial states. To further explore the advantage of the proposed MWCS, we realize its analog circuit using commercially available electronic elements. The results demonstrate that in comparison to traditional MWCSs, our circuit implementation greatly reduces the consumption of electronic components. This makes the MWCS more suitable for many chaos-based engineering applications. Furthermore, we propose an application of the MWCS to chaotic image encryption. Histogram, correlation, information entropy, and key sensitivity show that the simple image encryption scheme has a high security and reliable encryption performance. Finally, we develop a field-programmable gate array test platform to implement the MWCS-based image cryptosystem. Both theoretical analysis and experimental results verify the feasibility and availability of the proposed MWCS.
As convolution contributes most operations in convolutional neural network (CNN), the convolution acceleration scheme significantly affects the efficiency and performance of a hardware CNN ...accelerator. Convolution involves multiply and accumulate operations with four levels of loops, which results in a large design space. Prior works either employ limited loop optimization techniques, e.g., loop unrolling, tiling, and interchange, or only tune some of the design variables after the accelerator architecture and dataflow are already fixed. Without fully studying the convolution loop optimization before the hardware design phase, the resulting accelerator can hardly exploit the data reuse and manage data movement efficiently. This paper overcomes these barriers by quantitatively analyzing and optimizing the design objectives (e.g., memory access) of the CNN accelerator based on multiple design variables. Then, we propose a specific dataflow of hardware CNN acceleration to minimize the data communication while maximizing the resource utilization to achieve high performance. The proposed CNN acceleration scheme and architecture are demonstrated by implementing end-to-end CNNs including NiN, VGG-16, and ResNet-50/ResNet-152 for inference. For VGG-16 CNN, the overall throughputs achieve 348 GOPS and 715 GOPS on Intel Stratix V and Arria 10 FPGAs, respectively.
When chaotic systems are used in different practical applications, such as nonlinear control and cryptography, their complex chaos dynamics are strongly required. However, many existing chaotic ...systems have simple complexity, and this brings negative effects to chaos-based applications. To address this issue, this paper introduces a sine chaotification model (SCM) as a general framework to enhance the chaos complexity of existing one-dimensional (1-D) chaotic maps. The SCM uses a sine function as a nonlinear chaotification transform and applies it to the output of a 1-D chaotic map. The resulting enhanced chaotic map of the SCM has better chaos complexity and a much larger chaotic range than the seed map. Theoretical analysis verifies the efficiency of the SCM. To show the performance of the SCM, we apply SCM to three existing chaotic maps and analyze the dynamics properties of the obtained enhanced chaotic maps. Performance evaluations prove that the three enhanced chaotic maps have more complicated dynamics behaviors than their seed chaotic maps. To show the implementation simplicity of the SCM, we implement the three enhanced chaotic maps using the field-programmable gate array. To investigate the SCM in practical application, we design pseudorandom number generators using the enhanced chaotic maps.
Hardware/Software Co-Exploration of Neural Architectures Jiang, Weiwen; Yang, Lei; Sha, Edwin Hsing-Mean ...
IEEE transactions on computer-aided design of integrated circuits and systems,
2020-Dec., 2020-12-00, Letnik:
39, Številka:
12
Journal Article
Recenzirano
Odprti dostop
We propose a novel hardware and software co-exploration framework for efficient neural architecture search (NAS). Different from existing hardware-aware NAS which assumes a fixed hardware design and ...explores the NAS space only, our framework simultaneously explores both the architecture search space and the hardware design space to identify the best neural architecture and hardware pairs that maximize both test accuracy and hardware efficiency. Such a practice greatly opens up the design freedom and pushes forward the Pareto frontier between hardware efficiency and test accuracy for better design tradeoffs. The framework iteratively performs a two-level (fast and slow) exploration. Without lengthy training, the fast exploration can effectively fine-tune hyperparameters and prune inferior architectures in terms of hardware specifications, which significantly accelerates the NAS process. Then, the slow exploration trains candidates on a validation set and updates a controller using the reinforcement learning to maximize the expected accuracy together with the hardware efficiency. In this article, we demonstrate that the co-exploration framework can effectively expand the search space to incorporate models with high accuracy, and we theoretically show that the proposed two-level optimization can efficiently prune inferior solutions to better explore the search space. The experimental results on ImageNet show that the co-exploration NAS can find solutions with the same accuracy, 35.24% higher throughput, 54.05% higher energy efficiency, compared with the hardware-aware NAS.
Convolutional neural networks (CNNs) have become the dominant neural network architecture for solving many state-of-the-art (SOA) visual processing tasks. Even though graphical processing units are ...most often used in training and deploying CNNs, their power efficiency is less than 10 GOp/s/W for single-frame runtime inference. We propose a flexible and efficient CNN accelerator architecture called NullHop that implements SOA CNNs useful for low-power and low-latency application scenarios. NullHop exploits the sparsity of neuron activations in CNNs to accelerate the computation and reduce memory requirements. The flexible architecture allows high utilization of available computing resources across kernel sizes ranging from <inline-formula> <tex-math notation="LaTeX">1\times 1 </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">7\times 7 </tex-math></inline-formula>. NullHop can process up to 128 input and 128 output feature maps per layer in a single pass. We implemented the proposed architecture on a Xilinx Zynq field-programmable gate array (FPGA) platform and presented the results showing how our implementation reduces external memory transfers and compute time in five different CNNs ranging from small ones up to the widely known large VGG16 and VGG19 CNNs. Postsynthesis simulations using Mentor Modelsim in a 28-nm process with a clock frequency of 500 MHz show that the VGG19 network achieves over 450 GOp/s. By exploiting sparsity, NullHop achieves an efficiency of 368%, maintains over 98% utilization of the multiply-accumulate units, and achieves a power efficiency of over 3 TOp/s/W in a core area of 6.3 mm 2 . As further proof of NullHop's usability, we interfaced its FPGA implementation with a neuromorphic event camera for real-time interactive demonstrations.
As the emerging field of machine learning, deep learning shows excellent ability in solving complex learning problems. However, the size of the networks becomes increasingly large scale due to the ...demands of the practical applications, which poses significant challenge to construct a high performance implementations of deep learning neural networks. In order to improve the performance as well as to maintain the low power cost, in this paper we design deep learning accelerator unit (DLAU), which is a scalable accelerator architecture for large-scale deep learning networks using field-programmable gate array (FPGA) as the hardware prototype. The DLAU accelerator employs three pipelined processing units to improve the throughput and utilizes tile techniques to explore locality for deep learning applications. Experimental results on the state-of-the-art Xilinx FPGA board demonstrate that the DLAU accelerator is able to achieve up to 36.1× speedup comparing to the Intel Core2 processors, with the power consumption at 234 mW.
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