This paper proposes a new multilevel inverter (MLI) topology that utilizes trinary sequence for the dc sources. It gives maximum output voltage level with minimum dc source and switch count when ...compared to other sequences, such as symmetric, natural, binary, and quasi-linear. This is due to the fact that the trinary sequence generates of all additive and subtractive combinations of input dc levels in the output voltage waveform. The concept is implemented on a 9-level asymmetric MLI using only four active devices. Multicarrier unipolar pulsewidth modulation technique is adopted to create the switching pulses. Theoretical calculation of total harmonic distortion in both voltage and current waveforms has been performed using asymptotic time domain formula. These values are compared with simulation and experimental values for different modulation indices. Power loss calculation for proposed topology is discussed with appropriate mathematical equations.
Extra switching generates additional switching power loss, thus leading to the reduction of the efficiency of a system. Therefore, the article aims to reduce the switching power loss incurred owing ...to the extra switching in the transition of two carriers in the previously proposed strategy (RCMV1), which features reduced common-mode voltage and improved output harmonic distortion for a three-level neutral point clamped converter. First, a thorough analysis of extra switching in RCMV1 is presented. Second, based on this analysis and the two degrees of freedom in implementing a per-carrier switching sequence, two pulsewidth modulation schemes, namely RCMV1A-SLO and RCMV1B-SLO, are proposed to minimize the switching loss by online calculating the number of extra switchings between two switching sequences at the k th and ( k -1)th sampling instants, which determines which degree of freedom of the switching sequence at the k th instant yields the least number of commutations. Simulation and experimental results confirm an improvement of switching loss performance in RCMV1A-SLO and RCMV1B-SLO over RCMV1. Finally, a comparative analysis of output harmonic distortion between the two proposed schemes and the conventional phase opposition disposition is presented, demonstrating a superior harmonic performance of the two proposed ones over POD-SPWM.
This article proposes a decoupled control scheme for the modular multilevel converter (MMC) to reduce the total harmonic distortion (THD) and eliminate one specific harmonic. First, to realize the ...decoupled control between the ac and dc paths of the MMC, an improved nearest level control (INLC) method is proposed. It applies the round function to generate the ac output voltage levels, instead of the arm output voltage levels. Thus, a staircase wave is generated by the INLC method. Then, by adding an additional pulse to each quarter of the staircase wave, one specific harmonic can be eliminated without optimizing each conduction angle. Furthermore, a decoupled circulating current fuzzy control method is proposed to suppress the second-order harmonic and balance the arm energy. By this decoupled control structure, the output voltage and the circulating current can be controlled independently. Taking the fifth-order harmonic as an example, simulation and experimental results validate that the proposed scheme can simultaneously realize THD reduction and one specific harmonic elimination in the MMC output voltage.
In three-phase inverters, some modulation methods are used to reduce the high output common-mode voltage (CMV), which will bring many negative effects. However, the inverter with some reduced CMV ...(RCMV) methods may still have high spikes in some cases. This article proposes a new space-vector modulation (SVM), which is named 12-section SVM (12SSVM). The 12SSVM redivides the vector space into 12 sections to avoid the simultaneous switching of two legs in the areas of cross-section. This method can be used to eliminate the CMV spikes and be applicable in most modulation index ranges. The 12SSVM has a lower total harmonic distortion than other RCMV SVMs. The feasibility and effectiveness of the 12SSVM are verified by the simulations and experiments in a three-phase inverter.
This article proposes a parallel-connected 40-pulse diode rectifier (40PDR) based on a 20-pulse diode rectifier (20PDR) with a passive pulse multiplication circuit (PPMC) to mitigate harmonics. The ...PPMC deployed in this article is connected to the 20PDR dc-side and consists of a modified interphase transformer and two single-phase rectifiers. Since the proposed design only requires a low-capacity PPMC and does not need any switching and control circuits, the proposed 40PDR is a simple and low-cost solution. More importantly, using the proposed circuitry, the input current is almost sinusoidal; its input current total harmonic distortion is less than 1%. Simulations and experimental results reveal the proposed 40PDR's effectiveness in reducing harmonic distortion.
As a metric for measuring the combined space harmonic content of electric machine winding magnetomotive force (MMF), the winding total harmonic distortion (THD) is defined with an infinite series. ...Without truncation, the exact THD can be evaluated via a "family grouping" facilitated by a "family sum" over the fewest possible winding factors. Uniformly applicable to distributed windings and fractional-slot concentrated windings (FSCWs), this procedure also explains the inherent difference in harmonic content between both winding categories. Furthermore, the minimal THD (mTHD) that can be achieved by optimizing a winding is revealed with a closed-form expression. While intended for windings, the mTHD concept also benefits the design of low harmonic content rotor magnetic fields. Examples of both winding and rotor mTHD designs are provided.
This paper introduces a novel switched-capacitor-based 9-level inverter topology to meet IEEE standards for low total harmonic distortion (THD) in grid-connected inverters. The new design addresses ...the trade-off between increasing output voltage levels to reduce harmonics and the consequent rise in device count. The proposed topology is streamlined, consisting of 12 switches, 3 capacitors, 2 diodes, and a single DC source. Comparative analysis with similar topologies confirms the advantages of the new design. The experimental results show that the proposed inverter achieves a THD of 13.58% in its output voltage. The topology is validated through its application in a single-stage, three-phase photovoltaic system connected to the grid. Simulations are conducted using MATLAB/Simulink to test the system's performance. Furthermore, hardware-in-the-loop experiments are performed using OPAL-RT 5700 real-time simulators to further substantiate the efficacy of the proposed topology.
This paper presents a new islanding detection strategy for low-voltage inverter-interfaced microgrids based on adaptive neuro-fuzzy inference system (ANFIS). The proposed islanding detection method ...exploits the pattern recognition capability of ANFIS and its nonlinear mapping of relation between inputs. The ANFIS monitors seven inputs measured at point of common coupling (PCC), namely root-mean square (RMS) of voltage and current (RMS U and RMS I ), total harmonic distortion (THD) of voltage and current (THD U and THD I ), frequency (<inline-formula> <tex-math notation="LaTeX">{f} </tex-math></inline-formula>), and active and reactive powers (<inline-formula> <tex-math notation="LaTeX">{P} </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">{Q} </tex-math></inline-formula>) that are experimentally obtained based on practical measurement in a real-life microgrid. The proposed method is composed of passive monitoring of the mentioned inputs. It does not influence power quality (PQ) and considerably decreases non detection zones (NDZs). In order to cover as many situations as possible, minimize false tripping and still remain selective; type and number of samples are introduced. Here, one of the primary goals is reducing NDZ while keeping PQ in order. Based on the sampled frequency and number of samples, we find that the proposed method has less detection time and better accuracy when compared to the reported methods. Simulations performed in MATLAB/Simulink software environment and several tests performed based on different active load conditions and multiple distributed generation, prove the effectiveness, authenticity, selectivity, accuracy and precision of the proposed method with allowable impact on PQ according to UL1741 standard.
A CMOS single-pole double-throw (SPDT) antenna switch employing linearity-enhanced biasing strategy is proposed for the second-order harmonic (H2) reduction. It was implemented and demonstrated using ...a 0.28-lm thick-oxide MOSFET in 65-nm CMOS process. The NMOS transistor of the conventional antenna switch is replaced with the CMOS transistor composed of an NMOS and PMOS transistor in parallel to improve second-order harmonic distortion (HD2). The optimum channel width of an NMOS and PMOS transistor is chosen to achieve odd symmetry characteristic of I-V curve with respect to the drain-to-source voltage swing (VDS), and, as a result, enhance HD2 of the antenna switch. In addition, the linearity-enhanced biasing scheme is adopted to the PMOS transistor as a conventional negative biasing method of the NMOS transistor. This prevents the degradation of the power handling capability in adopting the PMOS transistor to the antenna switch. In the measurement, the proposed single-stack SPDT antenna switch shows an insertion loss of less than 0.6 dB and an isolation of greater than 38 dB from 100 MHz to 1 GHz with an input and output return loss of greater than 25 dB. Concerning for H2 and third-order harmonic (H3), it shows H2 of -65 dBm and H3 of -90 dBm at 150 MHz when a single-tone RF signal with a power of +5 dBm is applied. Compared to the conventional NMOS-based antenna switch, the proposed CMOS-based antenna switch improves HD2 by approximately 8 dB, 7 dB, and 1 dB at 150 MHz, 400 MHz, and 1 GHz, respectively, while maintaining the comparable insertion loss, isolation, and third-order harmonic distortion (HD3).
The article presents the analytical derivation of the minimum dc link capacitance in single-phase front ends with active power factor correction (PFC) without hold-up time requirements. Such systems ...typically employ boost-type rectifiers; operate under restricted total harmonic distortion (THD) of the grid-side current. Moreover, PFC rectifiers must be capable of tolerating step-like zero-to-rated load power variations. It is well known that these two constraints contradict each other, posing nontrivial design challenges. The revealed value of minimum capacitance is expressed by an explicit function of grid voltage and frequency, converter rated power, dc link voltage reference, and grid current THD and voltage loop phase margin set points. Experimental results validate the proposed methodology, closely matching corresponding analytical predictions.
