Disturbance observer proposed in this paper estimates the equivalent input disturbance and modifies control law to reject it. A reduced order observer is used to estimate disturbance from the ...input-output measurement when subject to large disturbance. Convergence of disturbance estimator is decided by the observer gain, which is selected through sufficient condition for stability. Simulation studies carried out on a satellite launch vehicle model has shown significant improvement on the response. The proposed controller has also shown enhanced disturbance rejection, when analyzed through frequency response of disturbance transfer function.
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A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip LEE, Pil-Ho; JANG, Young-Chan
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,
2019/06/01, Letnik:
E102.A, Številka:
6
Journal Article
Recenzirano
A 3Gbps/lane transmission buffer chip including a high-speed mode detector is proposed for a field-programmable gate array (FPGA)-based frame generator supporting the mobile industry processor ...interface (MIPI) D-PHY version 1.2. It performs 1-to-3 repeat while buffering low voltage differential signaling (LVDS) or scalable low voltage signaling (SLVS) to SLVS.
A scalable low-voltage signaling (SLVS) serial link transmitter for MIPI M-PHY is presented in this paper. It delivers 200–400 mV pp signals at date rates of 1.25–5.8 Gbps. The integrated circuit ...entity consists of the actual SLVS driver, an ADPLL-based clock synthesizer with a frequency multiplier, and an internal test signal generator with pseudo-random binary sequences. The circuit has been fabricated in a 40-nm CMOS process. The overall active die area is 0.2 mm
2
, while the actual driver occupies only 190 μm
2
. In this work it was confirmed that a low-power SLVS driver meets the stringent common-mode noise generation limits set for serial interfaces used in mobile devices. Noise power density remains below −138 dBm/Hz at all data rates. Total power consumption of the transmitter is kept low by utilizing dynamic CMOS pre-drivers and a low drop-out voltage regulator. It achieves power efficiency of 0.44–1.4 mW/Gbps with external clock and 2.6–4.7 mW/Gbps with clock synthesizer.
We have developed a diagonal 27.5mm 17.7M pixel 120frames/s CMOS image sensor with 34.8Gb/s readout. This sensor adopted new column counters for single-slope ADC that operate up to 2.376GHz and ...high-speed interface with embedded clock that achieves 2.376Gb/s per channel. Random noise is 2.75e-rms at 120frames/s. The dynamic range at 120frames/s reaches 77.6dB.
Design of 4Gbps SLVS-type transmitter in 55 nm CMOS Kadlubowski, Lukasz A.; Kmon, Piotr
2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems,
2017-June
Conference Proceeding
In this paper, the design of 4 Gbps, 2.25 mW Scalable Low-Voltage Signaling (SLVS)-type transmitter is described. The analysis of circuit performance is concentrated on the minimization of ...common-mode voltage disturbances, while providing satisfactory eye diagram parameters and low power consumption. The edge aligner circuit utilization is proposed in order to minimize the time delay between the input positive and the input negative control voltage of the driver. Moreover, the effectiveness of two methods for driver output impedance correction is evaluated. Special emphasis is put on a reliable transmission path modeling, whose parameters influence an overall transmitter operation. The designed transmitter will be fabricated in 55 nm CMOS technology.
This paper presents a MIPI (Mobile Industry Processor Interface) D-PHY (physical layer) analog part that meets the MIPI Alliance standard that supports high-speed (HS) transmitter (HS-TX) and ...receiver (HS-RX) modes as well as low-power (LP)-TX, LP-RX, and LP-contention detection (CD) modes. MIPI is a flexible, source synchronous serial interface standard connecting a host processor to display and camera modules on mobile devices. The standard supports signal levels of 1.2Vpp at 10Mbps in LP mode and 0.2Vpp at 80–1000Mbps in HS mode.
In the design, we propose the use of special circuits: LP-TX controls the slew-rate and limits current with a push–pull driver that reduces electromagnetic interference, LP-RX maintains good noise immunity using a hysteresis comparator and a set/reset (SR) latch, HS-TX supports synchronous differential high-speed data transmission based on Scalable Low Voltage Signaling (SLVS), and HS-RX stably receives transferred data with DC variations and AC noise using a very-wide-common-mode range differential amplifier (VCDA). We implemented the MIPI D-PHY analog chip using 0.13μm CMOS process under a 1.2V supply. We found that the HS-RX block shows a jitter of less than 5% at 1Gbps and a power consumption of 0.74mW that is suitable for the standard.
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► We designed MIPI D-PHY analog part meeting MIPI standard using 0.13μm CMOS process. ► The chip supports HS mode (HS-TX and HS-RX) and LP mode (LP-TX, LP-RX, and LP-CD). ► LP and HS signals have a 1.2V swing within 10Mbps and a 0.2V swing with 1000Mbps. ► LP-TX controls the slew-rate and limits current with a push–pull driver to keep EMI low. ► HS-RX chip shows jitter lower 5% at 1Gbps and 0.74mW power consumption.
