In this paper we classify the irreducible integrable modules for the twisted toroidal extended affine Lie algebras (twisted toroidal EALA, in short) with finite dimensional weight spaces when the ...finite dimensional center acts non-trivially. Using an automorphism we reduce to the case where K0 acts non-trivially and Ki, 1≤i≤n act trivially. Twisted toroidal EALA has a natural triangular decomposition and we prove that any irreducible integrable module of it with finite dimensional weight spaces is a highest weight module with respect to the above triangular decomposition. The highest weight space is an irreducible module for the zeroth component of the twisted toroidal EALA. We then describe the highest weight space in detail.
The open-winding configuration with a common dc bus provides a zero-sequence current loop which allows the zero-sequence current flowing. With the application in permanent magnet synchronous ...generator (PMSG) systems, the existing zero-sequence current is inevitably caused by the common mode voltage generated by pulsewidth modulation (PWM) techniques and the third back EMF by the inherent flux harmonic component. With the mathematical modeling analysis, the zero-sequence equivalent circuit based on the PMSG system is proposed. Meanwhile, a zero-sequence current suppression controller is designed. In this paper, a zero vector redistribution PWM technique is proposed. With this technique, the dwell times of zero vectors (000) and (111) for both converters are determined. Meanwhile, it gives the zero-sequence component overmodulation analysis. Both the control method and improved PWM technique are implemented in a 1-kW open-winding PMSG experimental setup, and the experimental results are discussed.
This paper investigates the influence of active zero vector pulsewidth modulation (AZPWM-1) and space vector pulsewidth modulation (SVPWM) on the design of passive common-mode (CM) attenuation ...methods to reduce CM current and shaft voltage in inverter-fed V/f-controlled induction motor drives. The passive CM attenuation methods examined here are the CM choke, the CM electromagnetic interference (EMI) filter, and the CM transformer. The attenuation requirement of AZPWM-1 and SVPWM is identified to design the passive CM choke and EMI filter. Based on the attenuation requirement, the design guidelines are revisited for SVPWM, and design rules are proposed for AZPWM-1. However, the CM transformer is designed based on the step change in magnitude of CM voltage of both the pulsewidth modulations (PWMs). The limitations in design, regarding switching frequency and component size for each case, are also established. It is shown that to have a similar attenuation in the considered two PWM cases, AZPWM-1 requires smaller passive components compared to SVPWM. The proposed design guidelines are substantiated with experimental results on a 1.1-kW induction motor drive.
Current-source converter (CSC) is more attractive and increasingly used to occasions with higher requirements for reliability due to inherent anti-short circuit ability. This paper combines the CSC ...with DC/DC converter to adapt to lower input voltage applications. However, rational allocation of the duty cycle for each switch to achieve the target voltage output and the increase of overall switching times brought by DC/DC converter are major problems. Proposed coordinated control strategy can reasonably take full advantage of degrees of freedom based on the adjustment variable to achieve accurately control of grid-side current and load voltage. In addition, dc-link current pulses according to 6 times grid angular frequency which avoids using the zero-vector to reduce the switching times. Experimental results show the proposed scheme can not only guarantees the power quality at grid side and precise voltage output, but also avoids using zero-vector.
The evolution of vehicle-to-grid technology introduces new challenges for high-performance ac-dc converters. This article proposes a zero-vector-reconfiguration based space vector pulse width ...modulation (SVPWM) technique for high-frequency link three-phase (HFLTP) ac-dc converter, which utilizes zero-vector reconfiguration to enable soft-switching and soft commutation in both rectifier and inverter modes. The proposed HFLTP ac-dc converter consists of a matrix converter (MC) and a full bridge converter (FBC), interconnected via a high-frequency transformer (HFT) to form a single-stage power converter with high power density and compact dimensions. The proposed modulation technique, which is based on SVPWM, reconfigures zero vectors to enable zero-voltage-switching for the FBC and zero-current-switching for the MC. Simultaneously, it suppresses voltage spikes of power devices and HFT without adding any auxiliary circuits. Notably, the proposed modulation strategy eliminates the necessity for current polarity detection, allowing for the application of the same switching sequence in both rectifier and inverter modes. To validate the efficacy and performance of the proposed modulation technique, a 160 Vdc-110 Vac, 1.2 kW prototype has been developed.
Parallel three-level inverters are widely used in high-power applications for increasing the power capacity of the system. However, when multiple three-level T-type inverters are connected to a ...single dc bus, the zero sequence circulating current (ZSCC) will be generated. For the operation of paralleled inverters, another requirement is to reduce the common mode voltage (CMV) associated with pulsewidth modulation (PWM) method. As these two issues are mutually coupled, the conventional space vector modulation (SVM) and active control methods reported so far cannot address them properly simultaneously. To overcome this limitation, a modified SVM technique is proposed to reduce the CMV, suppress ZSCC, and balance neutral point (NP) voltage. The generating mechanism of the ZSCC with respect to modulation scheme is analyzed. Based on the analysis, the large, medium, small, zero vector modulation method is proposed for reducing ZSCC and balancing the NP voltage with reduced CMV as the same in large, medium, zero vector modulation. Furthermore, the effectiveness of the proposed method is verified by comparing its results with those of the convectional PWM. The results are obtained from simulation and experiments.
This paper addresses the zero-sequence circulating current control in the multiparalleled three-phase voltage-source inverters. The model of the zero-sequence circulating current in the N-paralleled ...(N ≥ 3) inverters is derived. It is shown that the circulating current is not only susceptible to the mismatches of circuit parameters, but it is also influenced by the interactions of circulating current controllers used by other paralleled inverters. To eliminate these adverse effects on the circulating current control loop, a coordinate control strategy for the N-paralleled inverter is proposed based on the zero-vector feedforward method with the space-vector pulse width modulation. Moreover, a virtual inverter method is introduced to facilitate the implementation of the proposed controller, which decouples the interactions of circulating current controllers in the paralleled inverters. Finally, experimental results obtained from three-paralleled, grid-connected inverters validate the effectiveness of theoretical analysis and proposed approach. An effective mitigation of the circulating current is demonstrated for the paralleled inverters under the unequal operating conditions.
The advent of SiC devices which results in lower rise times and steep <inline-formula> <tex-math notation="LaTeX">\text{d}v/\text{d}t </tex-math></inline-formula> at the inverter terminal can ...compromise the common mode (CM)-conducted emissions' compliance, motor peak ac -CM currents, and leakage currents. Consequently, this results in a high ac and dc side CM filter weight. AC filters at the inverter output terminal are effective in reducing the slew rate of inverter voltage thereby reducing the peak CM current. However, a special case with high <inline-formula> <tex-math notation="LaTeX">\text{d}v/\text{d}t </tex-math></inline-formula> arising from low duty cycles is found to increase the peak ac-CM current significantly. Reduced CM voltage (CMV) schemes are popular pulsewidth modulation (PWM) methods to minimize the peak CMV but suffer from high <inline-formula> <tex-math notation="LaTeX">\text{d}v/\text{d}t </tex-math></inline-formula> under this special case as well. In this article, a staggered PWM scheme to minimize such peak ac -CM currents for a high-speed variable frequency drive (VFD) is evaluated using a three-level SiC-based T-type inverter as a demonstrator. From the analysis, the proposed switching pattern shows benefits over conventional sinusoidal PWM (SPWM) scheme and is found to be scalable to other PWM schemes and voltage levels. Simulation and experimental results are shown to validate the performance of the proposed switching pattern.
A counterexample to the lights out problem Nagy, János; Pach, Péter Pál
Journal of graph theory,
October 2022, 2022-10-00, 20221001, Letnik:
101, Številka:
2
Journal Article
Recenzirano
Odprti dostop
In this note we present a counterexample to the “lights out problem”, that is, for every odd prime
p $p$ we construct a simple graph
G $G$ with vertex set
V ${\mathscr{V}}$ such that there does not ...exist elements
x
v
∈
F
p
(
v
∈
V
) ${x}_{v}\in {{\mathbb{F}}}_{p}(v\in {\mathscr{V}})$ such that
∑
u
∈
N
v
x
u
≠
0 ${\sum }_{u\in Nv}{x}_{u}\ne 0$ for each
v
∈
V $v\in {\mathscr{V}}$. On the other hand, in the positive direction, we show that if a certain quadratic form
Q $Q$ is associated to the graph and the prime
p $p$ is positive definite, then the conjecture holds.
Pulse width modulation (PWM) converters generate switching common-mode voltages (CMV) across the load terminals. These voltages cause common mode currents, leading to bearing failure in motor loads ...and electromagnetic interference problems. This study proposes a novel space vector PWM strategy to reduce the CMV in the dual three-phase permanent magnet synchronous motor (PMSM) driven by two-level six-phase inverter. The novel space vector PWM algorithm discards the use of zero vectors. Firstly, the two largest voltage vectors of each sector are selected as main vectors to synthesise reference vector. Then, three groups voltage vector, which are opposite to the main vectors, have been selected as auxiliary vectors. Appropriate auxiliary vector selected is based on the length of zero voltage vector working time. Next, zero vector working time is distributed to the main and selected auxiliary vectors based on voltage-second principle. In addition, CMV and the harmonic component in z1z2 subspace of the proposed space vector PWM are analysed in detail. Finally, the expected CMV reduction to one-sixth of DC voltage and change rate of CMV in each cycle promised by the proposed novel space vector PWM are demonstrated with simulation and experimental results.
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