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Roshan-Zamir, Ashkan; Iwai, Takayuki; Yang-Hang Fan; Kumar, Ankur; Hae-Woong Yang; Sledjeski, Lee; Hamilton, John; Chandramouli, Soumya; Aude, Arlo; Palermo, Samuel
IEEE journal of solid-state circuits, 03/2019, Letnik: 54, Številka: 3Journal Article
This paper presents a four-level pulse amplitude modulation (PAM4) quarter-rate receiver that efficiently compensates for moderate channel loss in a robust manner through background adaptation of the receiver thresholds and equalization taps. The front-end utilizes an input single-stage continuous-time linear equalizer (CTLE) to boost the main cursor and relax the pre-cursor cancellation requirement, requiring only a 2-tap pre-cursor feed-forward equalizer (FFE) on the transmitter side. A 2-tap decision feedback equalizer (DFE) follows that includes one finite impulse response (FIR) tap and one infinite impulse response (IIR) tap to cancel first post-cursor and long-tail inter-symbol interference (ISI), respectively. In addition to the per-slice main three data samplers, a single error sampler is utilized for background threshold control and an edge-based sampler performs both phase-locked loop (PLL)-based clock and data recovery (CDR) phase detection and generates information for background DFE tap adaptation. Fabricated in general purpose (GP) 65-nm CMOS, the 56-Gb/s receiver achieves 4.63 mW/Gb/s and compensates for up to 20.8-dB loss at a bit error rate (BER) <; 10 -12 when operated with a 2-tap FFE transmitter.
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JCR | SNIP | JCR | SNIP | JCR | SNIP | JCR | SNIP |
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in: SICRIS
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