The article presents the analytical derivation of the minimum dc link capacitance in single-phase front ends with active power factor correction (PFC) without hold-up time requirements. Such systems typically employ boost-type rectifiers; operate under restricted total harmonic distortion (THD) of the grid-side current. Moreover, PFC rectifiers must be capable of tolerating step-like zero-to-rated load power variations. It is well known that these two constraints contradict each other, posing nontrivial design challenges. The revealed value of minimum capacitance is expressed by an explicit function of grid voltage and frequency, converter rated power, dc link voltage reference, and grid current THD and voltage loop phase margin set points. Experimental results validate the proposed methodology, closely matching corresponding analytical predictions.