This paper presents the first hardware implementation of the datagram transport layer security (DTLS) protocol to enable end-to-end security for the Internet of Things (IoT). A key component of this design is a reconfigurable prime field elliptic curve cryptography (ECC) accelerator that is 238<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> and 9<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> more energy-efficient compared to software and state-of-the-art hardware, respectively. Our full hardware implementation of the DTLS 1.3 protocol provides 438<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> improvement in energy-efficiency over software, along with code size and data memory usage as low as 8 and 3 KB, respectively. The cryptographic accelerators are coupled with an on-chip low-power RISC-V processor to benchmark applications beyond DTLS with up to two orders of magnitude energy savings. The test chip, fabricated in 65-nm CMOS, demonstrates hardware-accelerated DTLS sessions while consuming 44.08 <inline-formula> <tex-math notation="LaTeX">\mu \text{J} </tex-math></inline-formula>/handshake and 0.89 nJ/byte of the encrypted data at 16 MHz and 0.8 V.