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Higaki, N.; Kubosawa, H.; Ando, S.; Takahashi, H.; Asada, Y.; Anbutsu, H.; Sato, T.; Sakate, M.; Suga, A.; Kimura, M.; Miyake, H.; Okano, H.; Asato, A.; Kimura, Y.; Nakayama, H.; Kimoto, M.; Hirochi, K.; Saito, H.; Kaido, N.; Nakagawa, Y.; Shimada, T.
1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), 1999Conference Proceeding, Journal Article
A 4-way VLIW geometry processor runs at 312 MHz and contains a PCI/AGP bus bridge in a three-layer-metal CMOS process with 0.21 /spl mu/m design rules at 2.5 V. It features: (1) VLIW and SIMD instruction sets, (2) a software bypass mechanism, (3) special condition-code registers and branch condition generator for clipping, and (4) automatic clock delay tuning. The result is performance of 2.5 GFLOPS and 6.5 Mpolygons/s in a 3D geometry processor. This chip can be added to conventional graphics systems without requiring additional LSIs.
