This article reports a single-loop full-rate bang-bang clock and data recovery (BBCDR) circuit supporting a four-level pulse amplitude modulation (PAM-4) pattern. We eliminate both the reference and the separate frequency detector (FD) by deliberately adding two fixed strobe points in the bang-bang phase detector (BBPD) curve via a clock-selection scheme. As such, we can achieve a wide frequency-capture range in a single-sided FD polarity. The BBPD also incorporates a hybrid control circuit to automate the frequency acquisition over a wide frequency range. Prototyped in a 28-nm CMOS, the proposed BBCDR occupies a tiny area of 0.0285 mm 2 and exhibits a 23-to-29-Gb/s capture range. The acquisition speed 8.2 Gb/s/<inline-formula> <tex-math notation="LaTeX">\mu \text{s} </tex-math></inline-formula> and energy efficiency (0.68 pJ/bit) compare favorably with the state of the art.