Asynchronous circuits in general offer better voltage scalability compared to their synchronous counterparts due to the lack of clock and flexible timing requirement. NULL Convention Logic (NCL), a quasi-delay-insensitive asynchronous paradigm, is comprised of threshold gates as fundamental logic building components. The structure of these gates directly impacts performance and power aspects of the entire circuit. This paper introduces an alternative design methodology for NCL gates called logic transformation (LT) for supporting low operating voltages. Representative NCL gates and NCL components are implemented and presented to compare their performance. The results and analysis can be used by designers for selecting the most appropriate design for their specific applications.