Seven front-end boards (FEBs) equipped with the biggest Cyclone V E field-programmable gate array (FPGA) 5CEFA9F31I7N supporting eight channels sampled up to 250 MS/s at 14-bit resolution have been successfully installed in seven surface detectors (SDs) on the Pierre Auger Test Array. SDs use six channels with a sampling of 120 MHz. Two remaining channels with independent sampling at a 200-MHz rate were tested as radio channels. The FEBs have been developed without antialiasing filters to keep a maximal flexibility. Communication between SDs and the central data acquisition system (CDAS) has been established via a standard radio link without any modification of a standard protocol. Any tuning of required processes, typically being a task of the unified board, has been moved to the FPGA algorithm. The power consumption by the new FEBs is at the level of 18 W, but the average solar panel output power is ~10 W. An external power control circuit (with a hysteresis cut OFF/ON) supplies the entire SD electronics to avoid a total battery discharge and the possible damage this may cause. Such an interrupted operation reduces significantly the statistics of events recorded while a second (or larger) solar panel would eliminate this inconvenience, we gather experience here under realistic conditions on the Argentine pampas, including the reduced amount of available power. We installed seven FEBs in the Pierre Auger Test Array in November 2015. Data acquisition is going smoothly on the primary Auger (T1) trigger only. The time-over-threshold trigger has not been implemented due to instabilities.