This work presents a reconfigurable Gaussian noise generator using field-programmable gate array (FPGA). The Box-muller method is used, which is a very efficient algorithm and its statistic properties, such as mean and variant, are effectively achieved. Additionally, the square root computation based on the CODIC method is proposed. All algorithms are implemented in FPGA Virtex 6, ML605 board, from Xilinx. The main resource usages are 8% of the Number of occupied Slices, 5% of the Number of Slice LUTs, and only 1% of the Number of Slice Registers. The Gaussian noise generator result is represented by ChipSope Pro Analyzer, which runs in real-time with the clock speed of 100 Mhz. As can be observed, more than one million samples per second can be generated. The result is confirmed that the system works well and it is abatable for many applications; especially, in the area of fast-bit error rate (BER) tester in error correction technology, such as low-density parity-check (LDPC) and Polar code.