In this brief, a novel charge-domain 4T2C eDRAM-CIM macro is proposed that has three key features: 1) a novel 4T2C eDRAM cell with an enhanced PVT variation tolerance that resolves the limitations of previous eDRAM-CIM macros such as current domain operation, large bit-cell size, cell leakage, and low energy- and area-efficiency, resulting in high linearity (R2 = 0.9998) and 76.8% reduction in <inline-formula> <tex-math notation="LaTeX">3\sigma </tex-math></inline-formula> PVT variation, 2) a quarter-ADC-reduction scheme with an offset-calibration comparator that reduces the number of ADC by 73% while improving the accuracy drop by 7.82%, and 3) an array-embedded DAC that reduces the area overhead by 64.2% compared to current-based DAC. The proposed 4T2C eDRAM-CIM macro is fabricated in 65nm LP technology and achieves 43.02- to 49.20-TOPS/W and 2.4-TOPS/mm 2 when 4b<inline-formula> <tex-math notation="LaTeX">\times 4\text{b} </tex-math></inline-formula> MAC operation is performed with 250MHz. In addition, an 90.03% accuracy at the CIFAR-10 dataset with the ResNet-20 network is achieved.