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Chen, Kuan-Hung; Chen, Tse-An; Wei, Chia-Ling
IEEE solid-state circuits letters, 2020, Letnik: 3Journal Article
A high-accuracy pulse-based analog divider with 12-bit digital output is proposed in this letter. Moreover, a comparator-delay-free voltage-to-pulse generator (VPG) and a pulse divider (PDV) are proposed: the on-time of the VPG-generated pulses is proportional to its input voltage, and is free from comparator delay; the PDV performs the functions of a divider and an analog-to-digital converter, so the output of the proposed divider is 12-bit digital code directly. The proposed chip was fabricated using a 0.35-<inline-formula> <tex-math notation="LaTeX">{{\mu }}\text{m} </tex-math></inline-formula> 2P4M 3.3-V mixed-signal polycide process. According to the measured results, the maximal error is only 1.06% and the quiescent power is only 205 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula>.
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JCR | SNIP | JCR | SNIP | JCR | SNIP | JCR | SNIP |
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