In recent years, very fast dividers have been required for the real‐time application of digital signal processing, robot control, and the like. This paper proposes a high‐speed cellular array divider with a selection function that is based on the non‐restoring algorithm and can deal with both fixed‐point and negative operands in two's complement form. This divider uses new techniques that can generate in parallel both the quotient bit of one row and a partial remainder and CLS bit of the next row. The delay time of the proposed divider is calculated in terms of a delay of one unit such as a NAND gate. Finally, by using PARTHENON, a CAD (computer‐aided design) system for VLSI, this divider is designed and evaluated. As a result, elimination of the delay time for even rows becomes possible. Thus, the delay time can be decreased to approximately one half that of the high‐speed divider proposed by Cappa and Hamacher, which uses the most general high‐speed techniques of carry‐save and CLA.