•The transverse thermal resistance of chip was 1.25 times of the longitudinal thermal resistance.•The max temperature is 72.45 ℃, 43.15 ℃, 37.02 ℃ and 36.58 ℃ while the defect is missing bump and pad, missing bump, normal bump and bridge bump, respectively.•The normal bump and bridge bump are inspected by the max amplitude which the normal is 22.5 and the bridge is 26.5.•The state changed from solid to mushy and mushy to liquid when the time was 3.5 s and 8.45 s, respectively. Flip chip technology has been used extensively in microelectronic packaging due to the high density, fine spacing, smaller size. However, the size and spacing of the solder bumps are decreasing gradually, defect detection is getting more and more difficult. Thus, the growing demand for high reliability has generated considerable attention on the importance of defect inspection. This paper proposes an in-situ infrared thermography monitoring method with in situ monitoring system bases on modified thermal resistance network model that added the phase transition for the non-destructive analysis of packaging process. The different defects, such as missing bump and pad, missing bump, and bridge are inspected with an accuracy of up to 90 % based on in situ monitoring system. The maximum error between the model and the experiment is 27.6 %, while the minimum error is 13.6 %. The experiment results show that the max temperature of missing bump and pad, missing bump is 35.43 °C and 6.13 °C higher than normal, and the bridge is 0.44 °C lower than normal, respectively. The maximum amplitude by the Fourier transform is used to inspect due to the max temperature of normal and bridge are indiscernible, the results show that the bridge is 4 lower than normal. The model and experimental results show that the in-situ infrared thermography monitoring method is effective for detecting defects in high density electronic devices. The proposed method of in situ monitoring is expected to provide a new strategy for next generation of three-dimensional heterogeneous integrated chips defect inspection.