A novel capacitive structure embedding the FDSOI film serves as a test platform to extract Dit at top (film/BOX) and bottom (BOX/substrate) interfaces by a single CV/GV measurement. Fully depleted ...SOI (FDSOI) bare wafers interfaces quality is evaluated for the first time through CV/GVmeasurement and modeling and G/ω peaks fitting. The influence of FDSOI film thickness is evaluated on the specific G/ω peak amplitude related to top interface Dit.
The Four-Gate Transistor Cristoloveanu, S.; Blalock, B.; Allibert, F. ...
32nd European Solid-State Device Research Conference,
2002
Conference Proceeding
As the MOSFETs dimensions are scaled down, following the ITRS roadmap, the need for SOI wafers with ultra-thin Si films (UTF) becomes acute. Characterization of these wafers with simple, ...process-independent, and fast turnaround methods is very important. In this paper, we present for the first time 3 key aspects: (i) properties of UTF down to 10 nm thickness; (ii) comparison of thinning techniques (sacrificial oxidation vs. SCI); and (iii) comparison of pseudo-MOSFET and Hg-FET methods for UTF.
SOI Buried Oxide (BOX) electrical quality is assessed through Charge to Breakdown, Breakdown Voltage, low field leakage, BOX fixed charge density and BOX/Si interface trap density measurements. ...Breakdown electrical field higher than 10 MV.cm -1 and 10 years lifetime at operating voltages in excess of 16V are reported on thin BOX layers.
Elastic relaxation after Fin formation in intrinsically-strained materials was presented. Reported simulations are correlated with NBD strain measurements and are consistent with length dependence of ...drain current in sSOI FinFETs. Stress in the Fin's channel region depends on Fin length and height. dingle layer structured Fins are much more resistant to elastic relaxation than dual layer structured Fins, due to overall structure height. On dual layer structure Fins, significant relaxation is expected for LFin shorter than 750nm, while single layer structured Fins do not relax significantly until 300nm. For transistor layout, elastic relaxation effects should be modeled or circumvented. Fin Length effects need to be added to other layout effects in Spice models.
SOI FinFET versus bulk FinFET for 10nm and below Hook, Terence B.; Allibert, F.; Balakrishnan, K. ...
2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S),
2014-Oct.
Conference Proceeding
Peer reviewed
FinFETs may in principle be built on either bulk 1-3 or SOI 4-5 substrates. In this paper we will review some of the technical issues associated with choice of substrate, directly comparing empirical ...results on 10nm hardware for which all the other processes are as much the same as possible. Furthermore, we will discuss the challenges beyond the 10nm generation, where fundamental changes in materials may render the debate moot. Our conclusion and prognosis is that SOI was, is, and will continue to be the technically superior choice.
SAW resonators built on Smart Cut™ POI wafers are electrically and thermally stressed in order to assess their robustness and the evolution of their characteristics with the occurrence of domain ...inversion. It is shown that the coercive field is higher than expected, and that specific domain features develop above this threshold. The impact of physical evolution of the substrate on resonator figures of merit is discussed. POI, LTOI, SAW, resonators, ferroelectric domains, switching, stress.
We present for the first time the RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers. These wafers are fully compatible with the thermal budget of CMOS process. The investigated ...SOI wafers with a fixed BOX of 400 nm-thick show effective resistivity values higher than 4 kΩ-cm and harmonic distortion levels lower than -81 dBm for a 900 MHz input signal with +15 dBm, i.e. more than 95 dBc. Our investigations confirm the capability of trap-rich HR-SOI wafer for the integration of RF systems in Si.
This paper analyses the impact of 10nm Si cap layer for UTBB pFET eSiGe, with 35% Ge in channel and source/drain. For the first time, it is found that this Si cap can improve both access resistance ...and hole mobility in narrow structures.
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