In this work, we clarify the role of surface preparation on the buried channel properties. First, we demonstrate the efficiency of a forming gas anneal (FGA) to erase the difference between thin and ...thick films. Then, we investigate various combinations of surface treatments and their impact on the top surface and buried interface, separately.
From SOI materials to innovative devices Allibert, Frédéric; Ernst, Thomas; Pretet, Jérémy ...
Solid-state electronics,
05/2001, Volume:
45, Issue:
4
Journal Article
Peer reviewed
Novel device architectures and materials are required to extend the limits of ULSI microelectronics. Recent properties of UNIBOND
® and SOS substrates, determined with the pseudo-MOSFET technique are ...described. The discussion of advanced SOI devices includes two basic aspects: the scaling of conventional MOSFETs and the design of alternative structures. We discuss the effects resulting from the reduction in channel width, length and thickness and present the merits of more innovative transistors with ground-plane, dynamic-threshold or double-gate.
In this paper, GlobalFoundries' 22 nm fully depleted (FD) SOI process was run on standard and high-resistivity wafers with a designed PN junctions interface passivation solution to counter parasitic ...surface conduction (PSC) effects. Substrate quality is monitored in terms of effective resistivity (\rho_{\text {eff }}) and losses based on on-wafer measurements of coplanar waveguides (CPW), fabricated in either bottom or top metal layers. Several PN patterns are examined and they demonstrate effective passivation of the PSC, region separating the P- and N-doping regions show better performance, which can further be improved applying a reverse PN bias to widen the depletion regions. 50 \Omega \text{CPW} line designed with PN interface passivation achieves 0.15 dB/ mm lower propagation losses at 15 GHz than 50 \Omega thin-film microstrip line in this technology. Impact of substrate quality on a 5-20 GHz inductor is analyzed by comparing substrates with standard resistivity, high-resistivity with PSC and high-resistivity with PN junction solution, showing an upto 62% improvement in quality factor.
This paper evaluates the small- and large-signal characteristics of a single pole double thru (SPDT) RF antenna switch including its insertion loss, isolation and non-linear behavior. It is ...fabricated on two different types of high resistivity (HR) Silicon-on-Insulator (SOI) substrates: one standard (HR-SOI) and one trap-rich (RFeSI80). Using a special test structure, the contribution of substrate and active devices is separated for both in small- and large-signal. It is shown that by using trap-rich substrate technology, a reduction of more than 17 dB of 2 nd harmonic is achieved compared with HR SOI substrate.
Double-gate MOSFETs: performance and technology options Cristoloveanu, S.; Allibert, F.; Zaslavsky, A.
2001 International Semiconductor Device Research Symposium. Symposium Proceedings (Cat. No.01EX497),
2001
Conference Proceeding
The advantages of double-gate (DG) SOI MOSFETs over conventional, single-gate transistors are described in terms of performance and potential for ultimate scaling. The peculiarity of DG-MOSFETs is ...that the top and bottom gates are biased simultaneously to establish equal surface potentials: V/sub G2/ = V/sub G1/ for identical gate oxides, or V/sub G2/ = V/sub G1/(t/sub 0X2//t/sub 0X1/) to compensate for the difference in front and back oxide thickness. In fully depleted transistors with a thin enough film, controlling the channel from both sides, forces most of the carriers to flow in the middle of the film, according to the volume inversion concept. Volume inversion results in excellent properties, which will be reviewed in this paper. In particular, the carrier mobility is enhanced, so that the transconductance in double-gate mode exceeds twice the value observed in single-gate mode. A DGMOSFET is more than the sum of two classical transistors.
SOI wafers have been used for digital applications for 2 decades. Historically separated between the high-performance, Partially Depleted (PDSOI) 1 and ultra-low power Fully Depleted (FDSOI) 2, the ...two architectures merged more recently into the UTBB-FDSOI (Ultra-Thin Body & BOX) technology 3. In order to maintain optimum device performance, the buried oxide (BOX) thickness has been scaled from 25nm (28nm node) to 20nm (22nm node). In this paper we present the benefits of further scaling the BOX to 15nm for the next node and describe the process used to fabricate such SOI wafers along with their physical and electrical properties.
In this paper, we investigate additional features of performance (parasitic capacitances, switching capability etc.) and applications of slightly asymmetric DG-MOSFETs. Our simulations indicate no ...major disadvantages to asymmetric 50/100nm DG.
We report FDSOI devices with a 20nm gate length (L G ) and 5nm spacer, featuring a 20% tensile strained Silicon-on-Insulator (sSOI) channel NFET and 35% Ge partially compressive strained ...SiGe-on-Insulator (SGOI) channel PFET. This work represents the first demonstration of strain reversal of sSOI by SiGe in short channel devices. At V dd of 0.75V, competitive effective current (I eff ) reaches 550/340 μA/μm for NFET, at I off of 100/1 nA/μm, respectively. With a fully strained 30% SGOI channel on thin BOX (20nm) substrate and V dd of 0.75V, PFET I eff reaches 495/260 μA/μm, at I off of 100/1 nA/μm, respectively. Competitive sub-threshold slope and DIBL are reported. With the demonstrated advanced strain techniques and short channel performance, FDSOI devices can be extended for both high performance and low power applications to the 10nm node.
This paper discusses on the development of germanium-on-insulator (GeOI) structures made by using the smart cut technology, in the preparation of the donor wafer and on the Ge epi development. Thin ...single crystal layers of Ge 001 have been successfully transferred via oxide to oxide bonding or by Ge to oxide bonding, onto 100 mm and 200 mm Si substrates. The surface roughness of the wafers has been measured by AFM. The surface roughness originating from the splitting step is eliminated by a soft polishing step using a CMP.
