We report FDSOI devices with a 20nm gate length (L G ) and 5nm spacer, featuring a 20% tensile strained Silicon-on-Insulator (sSOI) channel NFET and 35% Ge partially compressive strained ...SiGe-on-Insulator (SGOI) channel PFET. This work represents the first demonstration of strain reversal of sSOI by SiGe in short channel devices. At V dd of 0.75V, competitive effective current (I eff ) reaches 550/340 μA/μm for NFET, at I off of 100/1 nA/μm, respectively. With a fully strained 30% SGOI channel on thin BOX (20nm) substrate and V dd of 0.75V, PFET I eff reaches 495/260 μA/μm, at I off of 100/1 nA/μm, respectively. Competitive sub-threshold slope and DIBL are reported. With the demonstrated advanced strain techniques and short channel performance, FDSOI devices can be extended for both high performance and low power applications to the 10nm node.
This paper discusses on the development of germanium-on-insulator (GeOI) structures made by using the smart cut technology, in the preparation of the donor wafer and on the Ge epi development. Thin ...single crystal layers of Ge 001 have been successfully transferred via oxide to oxide bonding or by Ge to oxide bonding, onto 100 mm and 200 mm Si substrates. The surface roughness of the wafers has been measured by AFM. The surface roughness originating from the splitting step is eliminated by a soft polishing step using a CMP.
For the first time, we report high performance hybrid channel ETSOI CMOS by integrating strained SiGe-channel (cSiGe) PFET with Si-channel NFET at 22nm groundrules. We demonstrate a record high speed ...ring oscillator (fan-out = 3) with delay of 8.5 ps/stage and 11.2 ps/stage at V DD = 0.9V and V DD = 0.7V, respectively, outperforming state-of-the-art finFET results. A novel "STI-last" integration scheme is developed to improve cSiGe uniformity and enable ultra high performance PFET with narrow widths. Furthermore, cSiGe modulates device V t , thus providing an additional knob to enable multi-V t while maintaining undoped channels for all devices.
Continuous CMOS improvement has been achieved in recent years through strain engineering for mobility enhancement. Nevertheless, as transistor pitch is scaled down, conventional strain elements (as ...embedded stressors, stress liners) are loosing their effectiveness 1. The use of strained materials for the channel to boost performance is thus essential. In this paper, we present an original multilevel evaluation methodology for stress engineering design in next-generation power-efficient devices. Fully-Depleted-Silicon-On-Insulator (FDSOI) is chosen as the ideal test vehicle, as it offers the advantage of sustaining significant stress within the channel without plastic relaxation (the thin channel staying below the critical thickness 2). Starting from 3D mechanical simulations and piezoresistive coefficient data, an original, simple, physically-based model for holes/electrons mobility enhancement in strained devices is developed. The model is calibrated on physical measurements and electrical data of state-of-the-art devices. Non-Equilibrium Greens Function (NEGF) quantum simulations of holes/electrons stress-enhanced mobility give physical insights into mobility behavior at large stress (~3GPa). Finally, the new strained-enhanced mobility model is introduced in an industrial compact model 3 to project evaluation at the circuit level.
The Pseudo-MOSFET is a very successful characterization technique which can be further enriched by adopting split-C(V) measurements for mobility evaluation. In this work, we investigate the impact of ...the effective surface on the accurate evaluation of gate-to-channel capacitance in Pseudo-MOSFETs. The surprising dependence of the effective area on the AC signal frequency has been analyzed and modelled for a configuration with an arbitrary number of needles.
Several studies have demonstrated that floating body effects in partially-depleted SOI-CMOS technology can have a beneficial impact on the performance of digital circuits (Cristoloveanu and Li, 1995; ...Gautier et al., 1997). Nevertheless, the electrical characterization of transient phenomena is a difficult problem because the associated time constants can be close to a few nanoseconds. Direct measurement of the transient drain current (overshoot and undershoot) require a dedicated instrumental set-up (Jenkions et al., 1997) and do not correspond to the real conditions of IC operation (Wei et al., 1998). We propose an indirect method to measure the transient behavior of MOSFET drain current with a switching gate. The purpose of this work is to correlate the transistor time constants with the variation of the average drain current as a function of the switching frequency. The advantage of measuring the average current is to accurately reflect the transistor operation in logic circuits.
We present our recent achievements on 200mm GeOI formation from bulk Ge wafers and the resulting device characteristics. Pseudo-MOS measurements were done at Soitec, and Ge MOSFET fabrication was ...done at LETI and IMEC from epitaxial and bulk Ge starting materials, respectively.
The pseudo-MOSFET (Ψ-MOSFET) (Fig. 1) has constantly been used for studying the electrical properties of as-fabricated fully depleted SOI wafers. Two recent challenges drive the research: (i) ...extension to other types of electrical measurements and (ii) application to ultrathin SOI structures. We recently addressed the first challenge by proving the possibility of low-frequency noise (LFN) measurements with Ψ-MOSFET 1. In this paper, we investigate for the first time the Ψ-MOSFET noise in ultrathin films (down to 12 nm) and BOX (down to 10 nm).
In this paper, a non-self-aligned planar process is proposed. With this process, transistors are intrinsically asymmetric, but such MOSFETs have been shown to provide interesting back-gate ...field-induced series resistance lowering The planar architecture on SOI wafers enables a good control of silicon thickness. Ultrathin films are indeed crucial for achieving volume inversion and reducing short-channel effects without increasing the film doping. We focus on the preparation and characterization of fullsheet ultra-thin films. For the first time, the electrical properties of 10-nm-thick films have been measured in situ by adapting the pseudoMOSFET method.
