This article aims to provide deep insight into the physics of substrates for RF applications under large-amplitude signal excitations. The impact of physical parameters on substrate-induced harmonic ...distortion is modeled and well understood, from a theoretical and quantitative standpoint. This article formulates the interplay between applied voltage signal (dc or RF), interface fixed charge, and trapped charge in a charge-balance analysis for high-resistivity and trap-rich (TR) substrates. A TCAD approach gives strong insight into the impact of such semiconductor material and interface properties on the RF substrate's effective resistivity and linearity. First, a static analysis reveals how TR interface passivation overcomes the parasitic surface conduction effect using the concept of deep Fermi-level pinning. Next, substrates are analyzed in response to dynamic excitation signals. Using step functions to pulse an MOS structure from strong negative to strong positive applied charge sheds light on carrier dynamics. The characteristic time constants associated with variations in trap occupancy and in free carrier densities are discussed. Finally, sinusoidal large-amplitude signals are considered to analyze harmonic distortion from several types of substrates at various RF frequencies.
This article presents the accurate modeling results of the nonlinear behavior of a wide range of silicon-based substrates at RF. The TCAD-based model includes carrier inertia effects and captures the ...transient nonequilibrium phenomena in the semiconductor substrate regions in response to a large-amplitude RF signal. The model is applied to coplanar waveguide (CPW) lines measured on 19 different silicon-based samples that have key differences in their material and interface parameters, such as different values for nominal doping, interface oxide charge, the presence or not of a trap-rich passivation layer, and characteristic dimensions. Furthermore, the CPW line's distortion levels are measured from 25 °C up to 175 °C and at five fundamental frequencies under large-signal excitation from 50 MHz to 5.4 GHz. An excellent model to experiment correlation is achieved under all of these conditions, and the impact of the material and excitation parameters are discussed with strong physical insight provided by the simulation tool.
► Implementation of a novel characterization technique for bare SOI, based on split C-V measurement using pseudo-MOSFET. ► The effective mobility of electrons and holes is obtained from low-frequency ...split C-V measurements. ► Excellent agreement was obtained between effective mobility curves from Id (Vg) and from split C-V. ► The impact of surface passivation on the effective mobility was confirmed. ► The electron mobility can exceed 500 cm2V–1s–1 in thin SOI films with passivated surface.
We demonstrate for the first time the feasibility of split C–V measurements on as-fabricated SOI wafers using pseudo-MOSFET configuration. An adapted methodology to determine the effective mobility of electrons and holes by split C–V technique is proposed and validated through comparison with the effective mobility extracted from static measurements. The method has been applied to different SOI materials (thin and thick film/BOX, passivated and non-passivated surface). The frequency and substrate depletion effects and the role of probe pressure and spacing are discussed. The electron mobility can exceed 500cm2V−1s−1 in thin SOI films with passivated surface.
The first part of this paper deals with the standard etching techniques (Secco, Schimmel, Wright etch…) used for defects delineation in Si, SiGe, Ge and in new engineered substrates made from these ...starting materials, such as Silicon-on-Insulator (SOI), strained and extra-strained Silicon-on-Insulator (sSOI and XsSOI) and Ge-on-Insulator (GeOI). We focus in the second part on the new, chromium-free etching techniques which have recently been developed: chemical solutions containing other oxidizing agents (such as organic peracids, additional compounds such as bromine, iodine etc.) and gaseous HCl etching. We compare the performances of standard etching solutions with those of chromium-free etching techniques and list the specificities of the different techniques. Finally, we attempt to link defect etching results with those coming from physical characterization techniques (such as Raman spectroscopy, X-ray diffraction and Pseudo-MOSFET mobility measurements). A few similar studies can be found in the literature. Extensive work is however still necessary to establish a proper correlation between selective etching and those techniques. Up to now, defect selective etching techniques are the most sensitive ones for an accurate evaluation of crystalline quality.
► Biasing the back interface in accumulation while extracting carrier mobility in FD-SOI MOSFETs leads to underestimated values. ► Apparent mobility degradation with decreasing film thickness in ...ultra-thin SOI MOSFET or Pseudo-MOSFET measurement is due to an additional component of the vertical electric field. ► In Pseudo-MOSFET measurements, the additional component of the vertical electric field comes from the traps and charges at the free-surface of the sample. ► We propose a new model to take this additional component of the vertical electric field into account.
The mobility-thickness dependence in SOI films is clarified. Measurements in fully depleted SOI MOSFETs show that the low-field mobility at the front channel decreases by thinning the Si film or by sweeping the back gate from depletion into accumulation. We demonstrate that this mobility degradation is only apparent, being related to the potential value at the surface facing the channel. This opposite-surface potential induces an intrinsic vertical field which adds to the usual gate-related field. The mobility drop simply indicates a deviation from the low-field condition which cannot be achieved. We propose an updated model for proper extraction and interpretation of the low-field mobility. Pseudo-MOSFET results reveal the existence of a similar additional vertical field in bare SOI wafers, induced by charges present on the unpassivated surface. This intrinsic field increases in thinner films and affects pseudo-MOSFET conduction. The mobility decrease measured in SOI wafers with thinner films reflects the increasing impact of the intrinsic field and does not imply any degradation in quality of film-BOX interface.
The left figure shows noise spectrum in SOI wafers, where 1
/f noise behavior is obtained. Inset: pseudo-MOSFET configuration used in noise measurements for the first time. The right figure indicates ...that noise level is almost pressure-independent and the curves follow the carrier number fluctuation model.
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► Noise measurements at wafer level were performed using the pseudo-MOSFET configuration. ► 1
/f noise behavior in relatively thick and ultra-thin SOI layers is obtained. ► No probe pressure dependence of the noise is observed in non-passivated wafers. ► Noise measurements offer a better sensitivity in qualifying silicon-SiO
2 interfaces.
Low-frequency noise (LFN) is generated by interactions of the channel carriers with interface traps and oxide charges. Therefore, noise measurements on silicon on insulator (SOI) wafers can give important information about the state of the interfaces and their defect density. Here, noise measurements at wafer level were performed using the pseudo-MOSFET (
Ψ-MOSFET) configuration. 1/
f noise behavior in relatively thick and ultra-thin SOI layers is obtained. No probe pressure dependence of the noise is observed. The influence of wafer surface states is showed and further confirmed in passivated SOI samples. Origins of noise generation are discussed.
•This paper shows the potential of buried PN junctions as a substrate interface passivation solution to increase the effective resistivity (ρeff) figure of merit of a High-Resistivity (HR) substrate ...suffering from Parasitic Surface Conduction layer (PSC).•We demonstrate that this method can be implemented using an industrial process with an effective resistivity reaching 2 kΩ.cm with 0.1 dB/mm loss at 6 GHz for a HR + PN substrate.•Temperature, dose and implantation energy variations were performed in order to identify the buried PN junctions robustness. At high-temperature, HR + PN substrate still shows an enhancement of RF performance.
In this paper, we aimed to show the potential of buried PN junctions as a substrate interface passivation solution to increase the effective resistivity (ρeff) figure of merit of a High-Resistivity (HR) substrate suffering from Parasitic Surface Conduction layer (PSC). We characterize Coplanar Waveguides (CPW) in order to monitor the substrate frequency response. We demonstrate that this method can be implemented using an industrial process with an effective resistivity reaching 2 kΩ.cm with 0.1 dB/mm loss at 6 GHz for a HR + PN substrate. PN pattern, temperature and implantation conditions varations were performed in order to identify the buried PN junctions robustness. At high-temperature, HR + PN substrate still shows an enhancement of RF performance. Contrary to HR w/o PN, HR + PN is bias independent. This method is suitable for local PSC passivation, targeting advanced SoC (System-on-Chip) in FD-SOI technology for next wireless communication generations and embedded RF electronics.
Bias Instability is a reliability issue affecting the threshold voltage of a MOS transistor when the gate is stressed with relatively high voltage. For the first time, we characterize the instability ...of bare SOI wafers using a Pseudo-MOSFET configuration. The effect of positive and negative stress pulses on the properties of both hole and electron channels is systematically investigated. The origins of the instability, the dependence of the degradation with time, and the recovery after the stress have been discussed.dependence
Domain reversal induction by a vertical electric field is studied at various temperatures in POI substrates. Extensive electrical and physical characterization is used to establish a correlation ...between stress conditions, switched domains area ratio and resonator performance. A tentative explanation is given for the unusual domain switching mechanism.
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