Neurobiological systems continually interact with the surrounding environment to refine their behaviour toward the best possible reward. Achieving such learning by experience is one of the main ...challenges of artificial intelligence, but currently it is hindered by the lack of hardware capable of plastic adaptation. Here, we propose a bio-inspired recurrent neural network, mastered by a digital system on chip with resistive-switching synaptic arrays of memory devices, which exploits homeostatic Hebbian learning for improved efficiency. All the results are discussed experimentally and theoretically, proposing a conceptual framework for benchmarking the main outcomes in terms of accuracy and resilience. To test the proposed architecture for reinforcement learning tasks, we study the autonomous exploration of continually evolving environments and verify the results for the Mars rover navigation. We also show that, compared to conventional deep learning techniques, our in-memory hardware has the potential to achieve a significant boost in speed and power-saving.
In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back ...end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 °C during a couple of hours. Then, the full LT process flow with process modules developed at 500 °C is exposed. Great progress and breakthrough for high performance (HP) digital stacked FETs has been made recently. Areas previously considered as potential showstoppers have been overcome: 1) efficient contamination containment for wafers with Cu/ultra low-<inline-formula> <tex-math notation="LaTeX">{k} </tex-math></inline-formula> (ULK) iBEOL enabling their reintroduction in front end of line (FEOL) for top FET processing; 2) low-resistance poly-Si gate for the top FETs and solutions for improving gate-stack reliability; and 3) full LT raised source drain (RSD) epitaxy including surface preparation combined with SiCO 400 °C spacer and SPER junctions activation. Finally, the first functional nMOS and pMOS demonstration with a 500 °C thermal budget (TB) is highlighted.
16-kb 1T-1C ferroelectric random access memory (FeRAM) arrays are demonstrated for 130-nm node technology with TiN/HfO 2 :Si/TiN ferroelectric capacitors integrated into the back-end-of-line (BEOL). ...The 0- and 1-state distributions measured on the arrays demonstrate perfect yield at 4.8-V operation, with extrapolations suggesting that the memory window (MW) is still open at six-sigma statistics. A programming speed down to 4 ns at 4 V is highlighted at the array level, together with an endurance up to <inline-formula> <tex-math notation="LaTeX">10^{{7}} </tex-math></inline-formula> cycles. Promising data retention up to <inline-formula> <tex-math notation="LaTeX">10^{{4}} </tex-math></inline-formula> s at 125 °C is measured on the arrays and, for the first time, solder reflow compatibility is demonstrated for HfO 2 -based FeRAM. The MW on 16-kb arrays remains open when using a 2.5-V programming voltage and when the capacitor area is decreased from 0.36 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}^{{2}} </tex-math></inline-formula> down to 0.16 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}^{{2}} </tex-math></inline-formula>, with a calculated programming energy lower than 100 fJ/bit. These results pave the way to competitive ultralow-power embedded nonvolatile memories (NVM) at more advanced nodes.
We analyze 2–5 μm spectroscopic observations of the dust coma of comet 67P/Churyumov-Gerasimenko obtained with the Visible InfraRed Thermal Imaging Spectrometer (VIRTIS-H) instrument on board Rosetta ...from 3 June to 29 October 2015 at heliocentric distances rh = 1.24–1.55 AU. The 2–2.5 μm color, bolometric albedo, and color temperature were measured using spectral fitting. Data obtained at α = 90° solar phase angle show an increase in bolometric albedo (0.05–0.14) with increasing altitude (0.5–8 km), accompanied by a possible marginal decrease in color and color temperature. Possible explanations include dark particles on ballistic trajectories in the inner coma and radial changes in particle composition. In the phase angle range 50°–120°, phase reddening is significant (0.031%/100 nm deg−1) for a mean color of 2%/100 nm at α = 90°, which might be related to the roughness of the dust particles. Moreover, a decrease in color temperature with decreasing phase angle is also observed at a rate of ~0.3 K deg−1, consistent with the presence of large porous particles, with low thermal inertia, and showing a significant day-to-night temperature contrast. Comparing data acquired at fixed phase angle (α = 90°), a 20% increase in bolometric albedo is observed near perihelion. Heliocentric variations in dust color are not significant in the time period we analyzed. The measured color temperatures vary from 260 to 320 K, and follow a rh−0.6 $r_{\textrm{h}}^{-0.6}$ r h −0.6 variation in the rh = 1.24–1.5 AU range, which is close to the expected rh−0.5 $r_{\textrm{h}}^{-0.5}$ r h −0.5 value.
The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile ...memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-all-around stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer.
Si doped HfO2 based ferroelectric capacitors integrated into Back-End-Of-Line (BEOL) 130 nm CMOS technology were investigated in regard to critical reliability parameters for their implementation in ...non-volatile one-transistor one-capacitor ferroelectric random-access memory applications. The assessed reliability parameters are electric field, capacitor area, and temperature and are evaluated on single and parallel structured capacitors to understand their respective impact on wake-up, fatigue, imprint, and retention.
We propose a TID effect hardening strategy for nanoscaled ultra-thin BOX and body SOI technologies. Experiments performed on NMOS and PMOS transistors demonstrate that TID effects can be mitigated by ...applying a dynamic back-bias technique. These data are used to calibrate the back-bias that has to be applied on UTSOI transistors to efficiently mitigate TID-induced effects. Elementary circuit cells made of inverters are then modeled using dedicated mixed TCAD calculations in order to validate the proof of concept of this hardening strategy at circuit level. Finally, results obtained on Ultra-Thin BOX devices typical of future FDSOI technologies show that the proposed hardening strategy efficiency increases with BOX thinning and then with technology downscaling.
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