Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary ...metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.
Quantum computation requires a qubit-specific measurement capability to readout the final state of individual qubits. Promising solid-state architectures use external readout electrometers but these ...can be replaced by a more compact readout element, an in situ gate sensor. Gate-sensing couples the qubit to a resonant circuit via a gate and probes the qubit's radiofrequency polarizability. Here we investigate the ultimate performance of such a resonant readout scheme and the noise sources that limit its operation. We find a charge sensitivity of 37 μe Hz(-1/2), the best value reported for this technique, using the example of a gate sensor strongly coupled to a double quantum dot at the corner states of a silicon nanowire transistor. We discuss the experimental factors limiting gate detection and highlight ways to optimize its sensitivity. In total, resonant gate-based readout has advantages over external electrometers both in terms of reduction of circuit elements as well as absolute charge sensitivity.
Spins in silicon quantum devices are promising candidates for large-scale quantum computing. Gate-based sensing of spin qubits offers a compact and scalable readout with high fidelity, however, ...further improvements in sensitivity are required to meet the fidelity thresholds and measurement timescales needed for the implementation of fast feedback in error correction protocols. Here, we combine radio-frequency gate-based sensing at 622 MHz with a Josephson parametric amplifier, that operates in the 500-800 MHz band, to reduce the integration time required to read the state of a silicon double quantum dot formed in a nanowire transistor. Based on our achieved signal-to-noise ratio, we estimate that singlet-triplet single-shot readout with an average fidelity of 99.7% could be performed in 1 μs, well below the requirements for fault-tolerant readout and 30 times faster than without the Josephson parametric amplifier. Additionally, the Josephson parametric amplifier allows operation at a lower radio-frequency power while maintaining identical signal-to-noise ratio. We determine a noise temperature of 200 mK with a contribution from the Josephson parametric amplifier (25%), cryogenic amplifier (25%) and the resonator (50%), showing routes to further increase the readout speed.
Hole spins in silicon represent a promising yet barely explored direction for solid-state quantum computation, possibly combining long spin coherence, resulting from a reduced hyperfine interaction, ...and fast electrically driven qubit manipulation. Here we show that a silicon-nanowire field-effect transistor based on state-of-the-art silicon-on-insulator technology can be operated as a few-hole quantum dot. A detailed magnetotransport study of the first accessible hole reveals a g-factor with unexpectedly strong anisotropy and gate dependence. We infer that these two characteristics could enable an electrically driven g-tensor-modulation spin resonance with Rabi frequencies exceeding several hundred mega-Hertz.
Self-heating in fully depleted silicon-on-insulator (FDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in ...a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase (<inline-formula> <tex-math notation="LaTeX">\Delta {T} </tex-math></inline-formula>) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature (<inline-formula> <tex-math notation="LaTeX">{T}_{\text {Device}} </tex-math></inline-formula>) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work.
In the standard MOSFET description of the drain current <inline-formula> <tex-math notation="LaTeX"> {I}_{{D}} </tex-math></inline-formula> as a function of applied gate voltage <inline-formula> ...<tex-math notation="LaTeX"> {V}_{{ {GS}}} </tex-math></inline-formula>, the subthreshold swing <inline-formula> <tex-math notation="LaTeX">{{SS(T)}}\equiv {{dV}}_{{{GS}}}/ {d}\log {I}_{ {D}} </tex-math></inline-formula> has a fundamental lower limit as a function of temperature <inline-formula> <tex-math notation="LaTeX">{T} </tex-math></inline-formula> given by <inline-formula> <tex-math notation="LaTeX">{ {SS(T)}}=\ln 10\,\, {k}_{ {B}} {T}/ {e} </tex-math></inline-formula>. However, recent low-temperature studies of different advanced CMOS technologies have reported SS (4 K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of SS(T) in 28 nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4 K. Until now, the increase of interface-trap density close to the band edge as temperature decreases has been put forward to understand the saturation. Here, an original explanation of the phenomenon is presented by considering a disorder-induced tail in the density of states at the conduction (valence) band edge for the calculation of the MOS channel transport by applying the Fermi-Dirac statistics. This results in a subthreshold <inline-formula> <tex-math notation="LaTeX"> {I}_{ {D}}\sim {e}^{{{ {eV}}}_{{{GS}}}/ {k}_{ {B}} {T}_{0}} </tex-math></inline-formula> for <inline-formula> <tex-math notation="LaTeX"> {T}_{0}=35 </tex-math></inline-formula> K with saturation value <inline-formula> <tex-math notation="LaTeX">{ {SS}}( {T}< {T}_{0})= \ln 10\,\, {k}_{ {B}} {T}_{0}/ {e} </tex-math></inline-formula>. The proposed model adequately describes the experimental data of SS(T) from 300 down to 4 K using <inline-formula> <tex-math notation="LaTeX"> {k}_{ {B}} {T}_{0} \simeq 3 </tex-math></inline-formula> meV for the width of the exponential tail and can also accurately describe <inline-formula> <tex-math notation="LaTeX">{ {SS}}( {I}_{ {D}}) </tex-math></inline-formula> within the whole subthreshold region. Our analysis allows a direct determination of the technology-dependent band-tail extension forming a crucial element in future compact modeling and the design of cryogenic circuits.
In this letter, we report the performance of high-κ /metal gate nanowire (NW) transistors without junctions fabricated with a channel thickness of 9 nm and sub-15-nm gate length and NW width. ...Near-ideal subthreshold slope (SS) and extremely low leakage currents are demonstrated for ultrascaled gate lengths with a high on-off ratio (I on /I off ) >; 10 6 . For the first time, an SS lower than 70 mV/dec is achieved at LG = 13 nm for n-type and p-type transistors, highlighting excellent electrostatic integrity of trigate junctionless NW MOSFETs.
► Conventional parameter extraction methodologies were revisited for the electrical characterization of JLT devices. ► Interestingly, two slopes in the Y-function of wide planar JLT devices were ...observed. ► Vth and Vfb of JLT devices were also extracted from two peaks in dgm/dVgf and dCgc/dVgf plots. ► The unique electrical properties of JLT devices are due to bulk neutral and surface accumulation channel. ► In addition, the variation of electrical parameters with gate length, doping level and back-gating in JLTs was discussed.
Several electrical parameters characterize device performance, electron transport and doping level in MOS transistors. In this paper, Junctionless Transistors (JLTs) fabricated on (100) silicon on insulator (SOI) wafer with 145nm thick BOX and 9nm silicon thickness were considered. Parameter extraction methodologies were revisited in order to account for the unique electrical properties of JLT devices. The deduced parameters, such as threshold voltage, flat-band voltage, drain induced barrier lowering (DIBL), low field mobility and channel doping level, are shown to reveal the specific features of JLT compared to conventional inversion-mode transistors.
We present a CMOS-compatible double gate and label-free C-reactive protein (CRP) sensor, based on silicon on insulator (SOI) silicon nanowires arrays. We exploit a reference subtracted detection ...method and a super-Nernstian internal amplification given by the double gate structure. We overcome the Debye screening of charged CRP proteins in solutions using antibodies fragments as capturing probes, reducing the overall thickness of the capture layer. We demonstrate the internal amplification through the pH response of the sensor, in static and real-time working modes. While operated in back-gate configuration, the sensor shows excellent stability (< 20 pA/min in the worst case), low hysteresis (< 300 mV), and a great sensitivity up to 1.2 nA/dec toward CRP proteins in the linear response range. The reported system is an excellent candidate for the continuous monitoring of inflammation biomarkers in serum or interstitial fluid.
PDF
