The epitaxial growth of germanium on silicon leads to the self-assembly of SiGe nanocrystals by a process that allows the size, composition and position of the nanocrystals to be controlled. This ...level of control, combined with an inherent compatibility with silicon technology, could prove useful in nanoelectronic applications. Here, we report the confinement of holes in quantum-dot devices made by directly contacting individual SiGe nanocrystals with aluminium electrodes, and the production of hybrid superconductor-semiconductor devices, such as resonant supercurrent transistors, when the quantum dot is strongly coupled to the electrodes. Charge transport measurements on weakly coupled quantum dots reveal discrete energy spectra, with the confined hole states displaying anisotropic gyromagnetic factors and strong spin-orbit coupling with pronounced dependences on gate voltage and magnetic field.
Spin-selective tunneling of holes in SiGe nanocrystals contacted by normal-metal leads is reported. The spin selectivity arises from an interplay of the orbital effect of the magnetic field with the ...strong spin-orbit interaction present in the valence band of the semiconductor. We demonstrate both experimentally and theoretically that spin-selective tunneling in semiconductor nanostructures can be achieved without the use of ferromagnetic contacts. The reported effect, which relies on mixing the light and heavy holes, should be observable in a broad class of quantum-dot systems formed in semiconductors with a degenerate valence band.
We report an electric-field-induced giant modulation of the hole g factor in SiGe nanocrystals. The observed effect is ascribed to a so-far overlooked contribution to the g factor that stems from the ...mixing between heavy- and light-hole wave functions. We show that the relative displacement between the confined heavy- and light-hole states, occurring upon application of the electric field, alters their mixing strength leading to a strong nonmonotonic modulation of the g factor.
The presented work concerns the manufacturing of very thin silicon wafers for a 3D Integrated Circuit industrial purpose. One of the key parameters of the 3D integration is the adherence of the ...bonded structure which involves silicon wafers and a polymer adhesive as an intermediate layer. The scope of the paper is to determine the suitable adherence of the stack for a successful manufacturing onto industrial tools. For this purpose the dismounting capacity of the fully automated equipment EVG®850DB depending on the adherence energy is studied. Direct and polymer bonded silicon pairs are prepared. Their energies of adherence cover a large range of energy: from 0.3 to 14 J/m2. The automatic mechanical dismounting process is successful when the stack adherence is 1.2 J/m2 or lower. This value does not depend on the bonded structure type: direct bonded pairs or thinned polymer bonded pairs exhibit the same behavior regarding the dismounting capacity. And we demonstrate that the industrial manufacturing of 70 μm thin silicon wafers is possible if the adherence is 0.4 J/m2 to 1.2 J/m2.
The study deals with the handling of thin wafers in 3D integration. It concerns the fabrication of 300 mm wafers in industrial tools. Usually, the manufacturing is based on a temporary bonding ...process performed at 200 °C using a thermoplastic adhesive. In that condition bonding, thinning and dismounting are satisfactory. Moreover, the adhesive flattening during bonding results in an excellent thickness uniformity of the bonded pairs, with a small total thickness variation (TTV) value suitable for 3D integration. If the temperature is 150 °C or lower, the adhesive thickness uniformity is not acceptable anymore. An innovative temporary bonding process at low temperature has thus been developed. It consists in a carrier fabrication with highly uniform adhesive thickness. The standard coated adhesive is flattened with a first reversible temporary bonding at 210 °C. After a first dismounting, this carrier is then bonded to the target device wafer with a low bonding temperature, from 110 °C to 150 °C. Due to the pre-flattening, 80 μm thick silicon films with an excellent TTV value can thus be obtained even with a low bonding temperature required by the device wafer. Moreover, after the device wafer thinning, the final dismounting can be performed without any antisticking layer.
The development of a silicon temporary carrier for thin wafer handling for 3D applications was investigated. Process selection and optimization ended up with a silicon carrier entirely covered with ...an antistick layer based on a fluorinated polymer. The carrier preparation was quite easy because only one coating was used and no sticking edge zone was needed onto the carrier. The fluorinated coating led to a very hydrophobic behavior. When bonded with a thermoplastic glue, it also exhibited very antiadhesive properties because the adherence was as low as 0.4J/m2 and lower than the adherence of a stack without any antiadhesive layer (above 4J/m2). The carrier was nevertheless suitable for different back side processes in 300mm: grinding, chemical cleaning, chemical mechanical polishing and silicon oxide deposition. Compared with a commercial carrier, it exhibited the same level of performance for the integration. The proposed carrier was compatible with a mechanical debonding of a thinned bonded structure with a silicon device wafer of 80µm. The carrier recycling was possible without any new preparation.
This paper concerns the study of a temporary bonding process: 3MTM Wafer Support System. This process is dedicated to the handling of thin silicon wafers with a glass carrier bonded with a UV curable ...polymer. The dismounting process is achieved after a laser treatment. Firstly, the 300mm bonding process leads to a very homogeneous bonded structure without any bonding defects. The morphology of the bonded structure is mainly dependent of the morphology of the glass. Secondly this process is also compatible with a back – grinding process and the thinned silicon structure can be processed up to 250°C. When using a blank silicon wafer, the 3MTM dismounting process (laser and peeling) leads to a silicon thin wafer without any cracks, chippings or adhesive traces. Finally the laser process can be removed from the debonding steps and a single mechanical dismounting process can be used.
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•A complete characterization of a silicon/glass temporary bonding for 3D integration is proposed•The bonded structure allows the handling of very thin silicon wafer (80μm)•Processes up to 250°C are compatible with the bonded structure
Copper–copper direct bonding is a fundamental procedure in three-dimensional integration. It has been reported that voiding occurs in bonded copper layers if process temperatures exceed 300°C; this ...leads to serious reliability issues. However, voiding nucleation and growth mechanisms have not been clearly established. Void characteristics were compared for different bonded structures specifically designed to identify the origin of void formation and its contribution. It seems that mechanical stress caused by different dilatation of silicon substrates and metal thin films leads to metallurgical creep. This stress-driven vacancy diffusion makes a major contribution to the reliability problem. This study provides better understanding of these physical phenomena and can be used as guideline for metal integration.
► Assembling materials or components for innovative applications. ► Low temperature (<500
°C) direct bonding processes. ► Review of key surface preparation parameters. ► Improvement shown through ...various processes as CMP or surface activation by plasma. ► Applications to bare or patterned surfaces for bonded heterostructure fabrication.
Low temperature direct bonding has been used extensively for assembling materials or components in the microelectronics and microsystem industries. We review here some key features of this technique both from the experimental and practical point of views. We give also some indications on the physical and chemical mechanisms involved in this attractive process, to better identify the important parameters impacting the quality and reliability of the technique. We describe mechanisms and report results on Si and SiO
2 bonding processes. Emphasis is put on improvements that allow obtaining strong and high quality bonding in low temperature process. We demonstrate that direct bonding can be applied as well to metal bonding, mainly to obtain conductive bonding, provided an efficient process can be used for surface preparation, e.g. CMP smoothing. More generally we show that direct bonding is well suited for many heterostructures via low temperature process for instance.
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