Diversity and inclusivity have guided many scholars of Hispanic Golden Age drama in their attempts to cover new ground and incorporate fresh insights in the first quarter of the twenty-first century ...on early modern theater written in Spanish. The six essays in this special issue provide a sampling of that spirit, exploring themes such as physical, ethnic, and political otherness, the dynamics of gender and caste in professional theater, and the ability of music to communicate transcendence and reconcile sacred and secular. Authors included are Glenda Nieto-Cuebas, Pablo García Piñar, Erin Cowling, Sharon Voros, Susan Paun de García, and J. Yuri Porras. They discuss the theatrical work of Lope de Vega, Calderón de la Barca, Sor Juana Inés de la Cruz, Juan Ruiz de Alarcón, Diego Sánchez de Badajoz, Ignacio Amestoy, Ainhoa Amestoy, Bernarda Ramírez, and Petronila Jibaja.
The time resolution of active pixel sensors whose timestamp mechanism is based on time-to-digital converters is critically linked to the accuracy in the distribution of the master clock signal that ...latches the timestamp values across the detector. The clock distribution network (CDN) that delivers the master clock signal must compensate process-voltage-temperature variations to reduce static time errors (skew) and minimize the power supply bounce to prevent dynamic time errors (jitter). To achieve sub-100-ps time resolution within pixel detectors and thus enable a step forward in multiple imaging applications, the network latencies must be adjusted in steps well below that value. Power consumption must be kept as low as possible. In this work, a self-regulated CDN that fulfills these requirements is presented for the FastICpix single-photon detector aiming at a 65-nm process. A 40-MHz master clock is distributed to <inline-formula> <tex-math notation="LaTeX">64\times64 </tex-math></inline-formula> pixels over an area of <inline-formula> <tex-math notation="LaTeX">2.4\times2.4 </tex-math></inline-formula> cm 2 using digital delay-locked loops, achieving clock leaf skew below 20 ps with a power consumption of 26 mW. Guidelines are provided to adapt the system to arbitrary chip area and pixel pitch values, yielding a versatile design with very fine time resolution.
A timing detector for the SHiP experiment Betancourt, C.; Dätwyler, A.; Serra, N. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
04/2019, Volume:
924
Journal Article
Peer reviewed
SHiP is a proposed general purpose fixed target experiment to be located at the CERN SPS accelerator. A fixed target station will be followed by magnetic shielding to reduce beam induced background, ...a dedicated tau neutrino detector and a detector to search for hidden particles beyond the Standard Model. Background taggers and a dedicated timing detector will ensure sufficient background rejection. The timing detector is required to have a timing resolution of 100 ps or less in order to reduce combinatorial di-muon background to an acceptable level. A proposed option for such a timing detector consists of plastic scintillating bars read out on each end by silicon photomultipliers, which is the focus of this study. We report on recent testbeam results carried out at CERN on single bars read out by an array of silicon photomultipliers and present a design for a prototype of the SHiP timing detector.
Cristóbal de Virués's La gran Semíramis features characters, images, and ideas that may be interpreted as grotesque. Recognizing this potential in the text, director Diego Chiri integrates visual and ...conceptual elements of this aesthetic into his 2015 Repertorio Español production of the play. In fact, three different types of grotesque are evident in the text and in Chiri's production, and all of them help to reconcile opposing, apparently contradictory ideas in the work. The ambivalent, simultaneous repulsion and attraction prompted by the abject, as conceived by Julia Kristeva, helps sustain in tension divergent views of the characters. Images and actions are subjected to processes of distortion, transformation, degradation, and parody, in the spirit of Mikhail Bakhtin's grotesque realism. The playwright and director reveal the machinations of power to be grotesque when wielded by vile sovereigns, as defined by Michel Foucault, and sanctioned by weak-minded administrators. An analysis of the Roman chronicles of Semiramis from which Virués draws his action reveals how, contrary to his sources, he has chosen to magnify the alleged controversial aspects of her persona to the extent that they overshadow her heroism. Virués's treatment of material from classical historians Diodorus and Justinus is characterized by the simultaneity of different modes of interpreting and representing the body and sexuality, and suggests that he participates in the processes of distortion and degradation that have typified the production of the Semiramis myth, itself grotesque, throughout the centuries.
In this paper, an FPGA-based plain delay line time-to-digital converters (TDC) is presented, together with a theoretical model on its timing properties. The TDC features an automated calibration ...system implemented in the on-chip processor of an SoC-FPGA, uses a low amount of FPGA resources and is therefore suitable for applications requiring a high number of channels, such as time-of-flight positron emission tomography (PET). We first investigated the importance of calibration and validated the theoretical model on the TDC timing properties. Finally, the device has been embodied into a two channel PET acquisition system and tested. We found the calibration essential to obtain a good time resolution (38-ps FWHM in comparison with a 78-ps FWHM obtained with the uncalibrated device). The model we developed is able to predict the TDC timing properties. They are shown to be related to the fundamental parameters of the used FPGA technology. In particular, the best achievable time resolution of this specific architecture (plain tapped delay line on FPGA) is set to about 30 ps by the sum of the setup and hold times of the registers in the FPGA. The timing resolution of the two-channel setup is about 118 ps.
This work reports on a novel effort to use Avalanche PhotoDiodes (APDs) to construct an active pixel detector for charged particles in collider experiments. A dual-beam Focused Ion Beam setup was ...used to characterize the response of the device. Results on the sensitivity of the guard structures separating pixels are compared to a detailed Monte Carlo simulation. These results suggest that, through control of the doping concentration, devices with a much improved fill factor can be achieved. A new technology is proposed that could elevate the fill factor to 100%.
In the study presented, we focus on the contribution of the front-end electronics to the single-photon time resolution, particularly for Silicon Photomultipliers. We investigate from a simple model ...for current sensing front-ends, the impact of parameters such as detector capacitance, parasitic inductance in the interconnection and input impedance (equivalent RLC network) in the slew-rate of the signal on one side, and the interaction of series and parallel noise with the detector capacitance on the other side. Design equations for optimum input impedance and optimum front-end bandwidth are proposed, as well as design criteria to discern between RC or RLC input network, since optimum parameters may differ depending on the sensor-ASIC interconnection: either multi-channel architectures where the ASIC inputs are wire bonded to standard Silicon Photomultipliers, or hybrid implementations with vertical 3D integration of sensor and front-end electronics.The later case can greatly exploit segmentation of large area detectors as a strategy to minimize the time jitter. The study presented highlights time jitter improvement using small Silicon Photomultipliers, proposing analytical expressions to estimate the minimum number of micro-cells sharing common readout electronics that minimize time jitter.
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