Self-aligned barriers are widely investigated either in replacement of dielectric liners to decrease the total interconnect
k value or as a treatment prior standard dielectric barrier deposition to ...improve reliability performances. In this paper, a technique based on the modification of the Cu surface is proposed. It consists first in removing native Cu oxide, then, enriching Cu surface with Si atoms followed by a nitridation step to complete the so called CuSiN self-aligned barrier. The dependency of Cu surface silicidation on Cu crystallographic orientation is described, evidencing two silicidation mechanisms: Si interstitial incorporation into Cu and Cu atoms substitution by Si atoms. He diluted in H
2 cleaning plasma prior to silicidation is demonstrated both to decrease Cu grain surface ability to silicidation compared H
2 plasma and to limit Si incorporation into Cu at grain boundaries. Compared to a standard SiCN barrier, CuSiN self-aligned barriers integrated as a treatment prior to SiCN evidenced at least four times longer lifetime under electromigration tests.
Basic physical properties as well as electrical and reliability performance of Infusion™ processing were evaluated. This approach, proposed as an alternative to CuSiN and electrolessly deposited ...Co-alloys, was shown to join the benefits of these two techniques without well-known associated drawbacks. Indeed, it is a uniform process, acting as an efficient Cu diffusion barrier, which does not require specific integration development. Different processes were introduced in a multi-level interconnect stack using ULK/USG stack as IMD, showing excellent electrical properties, and three times electromigration time-to-failure improvement with respect to standard SiCN barrier. However, it was shown that existing process conditions lead to some introduction of N atoms into ULK dielectric, showing there is still some room for process optimization in architectures using un-capped ULKs, to keep the benefits of EM improvement and aggressive effective dielectric constant.
Integration of CoWP self-aligned barriers in hybrid stack with SiCN liner in a standard 65
nm technology node integration scheme faces several issues. For example, bowing of upper metal level occurs ...due to the interaction between CoWP and etch plasma during SiCN opening step leading to lower line resistance compared to SiCN reference. Furthermore, wet cleaning after patterning step must be carefully processed in order to remove residues while keeping CoWP integrity. Electrical and reliability performance show that a clean recipe can be efficient to remove residues leading to low via resistance but in the same time, no electromigration improvement compared to SiCN reference is observed due to CoWP degradation and vice versa. To overcome integration issues, a new integration scheme called hybrid punch through (HPT) approach is proposed. In this approach, the patterning step is modified by SiCN open removal and it is followed by an adapted punch through process during metallization to open the via. HPT approach allows avoiding contact between CoWP and etch plasma or cleaning chemistry and leads to better electrical performance in terms of via and line resistances compared to standard scheme without degrading CoWP.
A new process, based on the interaction between Si and N rich gas cluster and post Cu CMP features surface, was integrated in a multi-level Cu interconnect stack using 65 nm design rules. Using the ...same integration scheme as stand-alone SiCN dielectric capping, excellent electrical properties were achieved when the process was implemented with a USG layer on top of a porous Ultra-Low K. Furthermore, 3x electromigration time to failure improvement was evidenced, making the approach very promising to address EM performance requirement for the most advanced technology nodes. Moreover, contrary to PE-CVD CuSiN approach, the process does not depend on Cu crystallographic orientation. Finally, when the implantation process is performed on un-capped ULK, a deep N contamination occurs. Therefore, the process must be optimized to preserve the interest of this technique for the most aggressive architectures.
The effect of post-oxidation treatments in nitric oxide (NO) on the interface defects in (100) Si/SiO2 is studied by EPR spectroscopy and nuclear analysis techniques. Results show that the interface ...structure is modified due to a self-limiting, localized incorporation of NO at the interface. The modified interface has an intrinsic interface defect density of less than or equal to 10 sup11 cm sup-2. NO thermal treatments open the possibility for the growth of H-free low defect density Si/SiO2 structures. 22 refs.
The NA48 collaboration is preparing a new experiment at CERN aiming to study
CP violation in the K
0-
K
0
system with an accuracy of 2 × 10
−4 in the parameter
R
e(ϵ′/ϵ). Decays in two
π
0's will be ...recorded by a quasi-homogeneous liquid krypton calorimeter. A liquid krypton calorimeter has been chosen to combine good energy, position and time resolution with precise charge calibration and long-term stability. The prototype calorimeter incorporating the final design of the electrode read-out structure is presented in this paper. An energy resolution of
≃3.5%
√E
with a constant term smaller than 0.5% has been obtained. The time resolution was found to be better than 300 ps above 15 GeV.
The DIRC particle identification system for the BaBar experiment Aleksan, R.; Amerman, L.; Aston, D. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
02/2005, Volume:
538, Issue:
1-3
Journal Article
Peer reviewed
Open access
A new type of ring-imaging Cherenkov detector is being used for hadronic particle identification in the BABAR experiment at the SLAC B Factory (PEP-II). This detector is called DIRC, an acronym for ...Detection of Internally Reflected Cherenkov (Light). This paper will discuss the construction, operation and performance of the BABAR DIRC in detail.
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