Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary ...metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.
Silicon spin qubits have emerged as a promising path to large-scale quantum processors. In this prospect, the development of scalable qubit readout schemes involving a minimal device overhead is a ...compelling step. Here we report the implementation of gate-coupled rf reflectometry for the dispersive readout of a fully functional spin qubit device. We use a p-type double-gate transistor made using industry-standard silicon technology. The first gate confines a hole quantum dot encoding the spin qubit, the second one a helper dot enabling readout. The qubit state is measured through the phase response of a lumped-element resonator to spin-selective interdot tunneling. The demonstrated qubit readout scheme requires no coupling to a Fermi reservoir, thereby offering a compact and potentially scalable solution whose operation may be extended above 1 K.
Spins in silicon quantum devices are promising candidates for large-scale quantum computing. Gate-based sensing of spin qubits offers a compact and scalable readout with high fidelity, however, ...further improvements in sensitivity are required to meet the fidelity thresholds and measurement timescales needed for the implementation of fast feedback in error correction protocols. Here, we combine radio-frequency gate-based sensing at 622 MHz with a Josephson parametric amplifier, that operates in the 500-800 MHz band, to reduce the integration time required to read the state of a silicon double quantum dot formed in a nanowire transistor. Based on our achieved signal-to-noise ratio, we estimate that singlet-triplet single-shot readout with an average fidelity of 99.7% could be performed in 1 μs, well below the requirements for fault-tolerant readout and 30 times faster than without the Josephson parametric amplifier. Additionally, the Josephson parametric amplifier allows operation at a lower radio-frequency power while maintaining identical signal-to-noise ratio. We determine a noise temperature of 200 mK with a contribution from the Josephson parametric amplifier (25%), cryogenic amplifier (25%) and the resonator (50%), showing routes to further increase the readout speed.
In the standard MOSFET description of the drain current <inline-formula> <tex-math notation="LaTeX"> {I}_{{D}} </tex-math></inline-formula> as a function of applied gate voltage <inline-formula> ...<tex-math notation="LaTeX"> {V}_{{ {GS}}} </tex-math></inline-formula>, the subthreshold swing <inline-formula> <tex-math notation="LaTeX">{{SS(T)}}\equiv {{dV}}_{{{GS}}}/ {d}\log {I}_{ {D}} </tex-math></inline-formula> has a fundamental lower limit as a function of temperature <inline-formula> <tex-math notation="LaTeX">{T} </tex-math></inline-formula> given by <inline-formula> <tex-math notation="LaTeX">{ {SS(T)}}=\ln 10\,\, {k}_{ {B}} {T}/ {e} </tex-math></inline-formula>. However, recent low-temperature studies of different advanced CMOS technologies have reported SS (4 K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of SS(T) in 28 nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4 K. Until now, the increase of interface-trap density close to the band edge as temperature decreases has been put forward to understand the saturation. Here, an original explanation of the phenomenon is presented by considering a disorder-induced tail in the density of states at the conduction (valence) band edge for the calculation of the MOS channel transport by applying the Fermi-Dirac statistics. This results in a subthreshold <inline-formula> <tex-math notation="LaTeX"> {I}_{ {D}}\sim {e}^{{{ {eV}}}_{{{GS}}}/ {k}_{ {B}} {T}_{0}} </tex-math></inline-formula> for <inline-formula> <tex-math notation="LaTeX"> {T}_{0}=35 </tex-math></inline-formula> K with saturation value <inline-formula> <tex-math notation="LaTeX">{ {SS}}( {T}< {T}_{0})= \ln 10\,\, {k}_{ {B}} {T}_{0}/ {e} </tex-math></inline-formula>. The proposed model adequately describes the experimental data of SS(T) from 300 down to 4 K using <inline-formula> <tex-math notation="LaTeX"> {k}_{ {B}} {T}_{0} \simeq 3 </tex-math></inline-formula> meV for the width of the exponential tail and can also accurately describe <inline-formula> <tex-math notation="LaTeX">{ {SS}}( {I}_{ {D}}) </tex-math></inline-formula> within the whole subthreshold region. Our analysis allows a direct determination of the technology-dependent band-tail extension forming a crucial element in future compact modeling and the design of cryogenic circuits.
We report the first experimental proof of concept of a new electromechanical adiabatic logic family operating without any kind of electrical and mechanical contacts. Based on comb-drive actuators and ...standard microelectromechanical system (MEMS) microfabrication, we demonstrate the cascadability of logic gates up to 170 °C, and operation in the kilohertz-range under a power supply of 4.5 V. Assuming that state-of-the-art microfabrication can downscale our MEMS gates by a factor of 100, we expect a dissipation of 0.1 aJ/op (24 <inline-formula> <tex-math notation="LaTeX">\text{k}_{\text {B}}\text{T} </tex-math></inline-formula>) at 250 kHz at 45 mV. This study paves the way toward new reliable low-power electromechanical digital circuits.
Three key metrics for readout systems in quantum processors are measurement speed, fidelity, and footprint. Fast high-fidelity readout enables midcircuit measurements, a necessary feature for many ...dynamic algorithms and quantum error correction, while a small footprint facilitates the design of scalable, highly connected architectures with the associated increase in computing performance. Here, we present two complementary demonstrations of fast high-fidelity single-shot readout of spins in silicon quantum dots using a compact, dispersive charge sensor: a radio-frequency single-electron box. The sensor, despite requiring fewer electrodes than conventional detectors, performs at the state of the art achieving spin readout fidelity of 99.2% in less than6μsfitted from a physical model. We demonstrate that low-loss high-impedance resonators, highly coupled to the sensing dot, in conjunction with Josephson parametric amplification are instrumental in achieving optimal performance. We quantify the benefit of Pauli spin blockade over spin-dependent tunneling to a reservoir, as the spin-to-charge conversion mechanism in these readout schemes. Our results place dispersive charge sensing at the forefront of readout methodologies for scalable semiconductor spin-based quantum processors.
Quantum shot noise probes the dynamics of charge transfers through a quantum conductor, reflecting whether quasiparticles flow across the conductor in a steady stream, or in syncopated bursts. We ...have performed high-sensitivity shot noise measurements in a quantum dot obtained in a silicon metal-oxide-semiconductor field-effect transistor. The quality of our device allows us to precisely associate the different transport regimes and their statistics with the internal state of the quantum dot. In particular, we report on large current fluctuations in the inelastic cotunneling regime, corresponding to different highly correlated, non-Markovian charge transfer processes. We have also observed unusually large current fluctuations at low energy in the elastic cotunneling regime, the origin of which remains to be fully investigated.
Extensive electrical characterization of ring oscillators (ROs) made in high-<inline-formula> <tex-math notation="LaTeX">{k} </tex-math></inline-formula> metal gate 28-nm fully depleted ...silicon-on-insulator technology is presented for a set of temperatures between 296 and 4.3 K. First, delay per stage (<inline-formula> <tex-math notation="LaTeX">\tau _{P} </tex-math></inline-formula>), static current (<inline-formula> <tex-math notation="LaTeX">{I} _{\textsf {STAT}} </tex-math></inline-formula>), and dynamic current (<inline-formula> <tex-math notation="LaTeX">{I} _{\textsf {DYN}} </tex-math></inline-formula>) are analyzed for the case of the increase of threshold voltage (<inline-formula> <tex-math notation="LaTeX">{V} _{\textsf {TH}} </tex-math></inline-formula>) observed at low temperature. Then, the same analysis is performed by compensating <inline-formula> <tex-math notation="LaTeX">{V} _{\textsf {TH}} </tex-math></inline-formula> to a constant, temperature-independent value through forward body biasing (FBB). Energy efficiency optimization is proposed for different supply voltages (<inline-formula> <tex-math notation="LaTeX">{V} _{\textsf {DD}} </tex-math></inline-formula>) in order to find an optimal operating point combining both high RO frequencies and low-power dissipation. We show that the Energy-Delay product can be significantly reduced at low temperature by applying an FBB voltage (<inline-formula> <tex-math notation="LaTeX">{V} _{\textsf {FBB}} </tex-math></inline-formula>). We demonstrate that outstanding performance of RO in terms of speed (<inline-formula> <tex-math notation="LaTeX">\tau _{P} = \textsf {37} </tex-math></inline-formula> ps) and static current (7nA/stage) can be achieved at 4.3 K with <inline-formula> <tex-math notation="LaTeX">{V} _{\textsf {DD}} </tex-math></inline-formula> reduced down to 0.325 V.
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