A single-ended transmitter achieves low power consumption with an integrated voltage modulation (IVM) scheme for memory interfaces. The transmitter preserves the power advantages of the ground ...(VSS)-terminated single-ended signaling by consuming no static power when transmitting logic-0s before the last bit of consecutive logic-0s (CLZs). All the intersymbol interference (ISI) accumulated during CLZs is compensated at once by the proposed IVM, which provides the unit interval (UI) spaced compensation voltage during the period of the last logic-0. The equalization, combining four-tap IVM and two-tap pull-up feed-forward equalization (FFE), allows the transmitter to be energy efficient without degrading the compensation effect. Per-UI basis IVM also has better immunity to noise and process, supply voltage, and temperature (PVT) variations than conventional phase equalization and pulsewidth modulation. The compensation effect and power consumption of IVM are also mathematically analyzed and compared with other conventional equalizations. A prototype chip fabricated in 65-nm CMOS has an area of 0.0168 mm2 and achieves a data rate of 16 Gb/s/pin over a transmission channel with −12.6 dB loss, with an energy efficiency of 0.85 pJ/bit.
Ergosterol peroxide is a natural compound of the steroid family found in many fungi, and it possesses antioxidant, anti-inflammatory, anticancer and antiviral activities. The anti-obesity activity of ...several edible and medicinal mushrooms has been reported, but the effect of mushroom-derived ergosterol peroxide on obesity has not been studied. Therefore, we analyzed the effect of ergosterol peroxide on the inhibition of triglyceride synthesis at protein and mRNA levels and differentiation of 3T3-L1 adipocytes. Ergosterol peroxide inhibited lipid droplet synthesis of differentiated 3T3-L1 cells, expression of peroxisome proliferator-activated receptor gamma (PPARγ) and CCAT/enhancer-binding protein alpha (C/EBPα), the major transcription factors of differentiation, and also the expression of sterol regulatory element-binding protein-1c (SREBP-1c), which promotes the activity of PPARγ, resulting in inhibition of differentiation. It further inhibited the expression of fatty acid synthase (FAS), fatty acid translocase (FAT), and acetyl-coenzyme A carboxylase (ACC), which are lipogenic factors. In addition, it inhibited the phosphorylation of mitogen-activated protein kinases (MAPKs) involved in cell proliferation and activation of early differentiation transcription factors in the mitotic clonal expansion (MCE) stage. As a result, ergosterol peroxide significantly inhibited the synthesis of triglycerides and differentiation of 3T3-L1 cells, and is, therefore, a possibile prophylactic and therapeutic agent for obesity and related metabolic diseases.
We combine 2-tap feed-forward amplitude equalization with phase equalization by 4-tap integrated pulse-width modulation. In a <inline-formula> <tex-math notation="LaTeX">\text{V}_{\mathbf {SS}} ...</tex-math></inline-formula>-terminated transmitter, amplitude equalization is selected for pull-up data transmission, and phase equalization for pull-down data transmission, and the strength of equalization can be controlled depending on channel losses. This combines the strength of amplitude equalization with the energy efficiency of phase equalization. A prototype quarter-rate transmitter for memory interfaces, fabricated in a 65nm CMOS process, performed single-ended signaling at a data-rate of 16Gb/s/pin over a channel with a loss of 14.7dB. Its energy efficiency is 1.04pJ/bit/pin and the figure-of-merit is 0.070pJ/bit/pin/dB.
In multi-lane interfaces using single-ended signaling such as memory interfaces, far-end crosstalk (FEXT) noise of the aggressor signal severely degrades signal integrity of the victim signal. A ...circuit for crosstalk cancellation (XTC) can reduce FEXT noise. However, the channel spacing makes the flight time difference between the forward and FEXT signals. As a result, the residual FEXT can remain. To further minimize the residual FEXT, this study proposes an XTC method to adjust the amplitude and timing independently. The timing is adjusted according to the passive element's value of the differentiator, and the amplitude is varied by using the high-frequency boosting circuit. Moreover, a continuous-time linear equalizer (CTLE) and a 1-tap decision feedback equalizer (DFE) are applied to reduce inter-symbol interference. A prototype chip of 2-lane receiver was fabricated in a 55-nm CMOS process to verify this scheme. Using the proposed XTC, CTLE, and 1-tap DFE, timing margins of 0.21 UI and 0.36 UI were achieved in 6-mil and 15-mil channel spacings at 6.4 Gb/s, both at a bit error rate of 10<inline-formula> <tex-math notation="LaTeX">^{-12}</tex-math> </inline-formula>.
The dual-rank configuration is one of the parallelization methods to increase the memory capacity for mobile applications. However, the stub mainly composed of the redistribution layer causes ...resonance reflections and its reflection interval reaches the bit period, which distorts signal and limits the signal bandwidth. A single-ended duobinary transmitter that utilizes the reflection is presented for dual-rank mobile memory interfaces where reflections dominate. The reflection is included in the transfer function for duobinary modulation, which allows the transmitter to have a wide eye opening and high energy efficiency. Two-tap reverse feed-forward equalization and slew-rate control are used to support the duobinary modulation in combination with the reflection. A prototype chip fabricated in a 65 nm CMOS process has an area of 0.0378 mm 2 and consumes 1.24 pJ/bit. It is verified at data rates of 8, 9 and 10 Gb/s/pin where the flight time of the 9 mm stub is 55.6 ps.
A single-ended four-level pulse-amplitude modulation (PAM-4) transmitter (TX) for memory interfaces achieves high signal integrity by combining an impedance-matched PAM-4 driver with a three-point ZQ ...calibration scheme. This improves PAM-4 linearity by allowing the driver to compensate for its impedance variation caused by the change in the drain-source voltage (<inline-formula> <tex-math notation="LaTeX">V_{\mathrm {DS}} </tex-math></inline-formula>) to suit the four output levels considering both the TX and the receiver (RX). Resistors and inductors are eliminated from the voltage-mode (VM) driver, reducing the area requirement. The two-tap asymmetric feed-forward equalization (FFE) allocates six different coefficients to each minimum pull-up and pull-down transition, compensating for nonlinear equalization strengths and asymmetric characteristics of the driver. A prototype chip fabricated in the 65-nm CMOS has an area of 0.0333 mm 2 and consumes 0.64 pJ/bit. It achieves a data rate of 28 Gb/s/pin with a ratio level separation mismatch (RLM) of 0.993.
The proposed single-ended transmitter for memory interfaces is an impedance-matched transmitter that utilizes a single ring-oscillator-based time-domain ZQ calibration. This ZQ calibration technique ...eliminates the offsets by using a gain-controlled ring oscillator with late-case forcing, resulting in low maximum/average error rates. The transmitter incorporates a phase equalization method to compensate for pre-cursor inter-symbol interference (ISI) without affecting the impedance matching achieved by ZQ calibration. This phase equalization is implemented by minimizing hardware to overcome the design complexity of conventional phase equalization and reduce power consumption. The prototype chip is fabricated in the 65-nm CMOS process. The transmitter and the ZQ calibration scheme occupy an area of 0.074 and 0.041 mm<inline-formula> <tex-math notation="LaTeX">^{2}</tex-math> </inline-formula>, respectively. The proposed ZQ calibration achieves a maximum error rate of 1.5% and an average error rate of 0.7%. In addition, the transmitter achieves an energy efficiency of 1.145 pJ/bit and an FoM of 0.11 pJ/bit/(dB/pin) at 12 Gb/s.
Next-generation sequencing (NGS) of the
(wood-rotting basidiomycete) genome was performed to identify carbohydrate-active enzymes (CAZymes). The resulting assembly (31 kmer) revealed a total length ...of 35,045,521 bp (49.7% GC content). Using the AUGUSTUS tool, 12,536 total gene structures were predicted by ab initio gene prediction. An analysis of orthologs revealed that 6806 groups contained at least one
protein. Among the 12,536 predicted genes,
contained 24 species-specific genes, of which 17 genes were paralogous. CAZymes are divided into five classes: glycoside hydrolases (GHs), carbohydrate esterases (CEs), polysaccharide lyases (PLs), glycosyltransferases (GTs), and auxiliary activities (AA). In the present study, annotation of the predicted amino acid sequences from
genes using the dbCAN CAZyme database revealed 508 CAZymes, including 82 AAs, 218 GHs, 89 GTs, 18 PLs, 59 CEs, and 42 carbohydrate binding modules in the
genome. Although the CAZyme repertoire of
was similar to those of other fungal species, the total number of GTs in
was larger than those of other basidiomycetes. This genome information elucidates newly identified wood-degrading machinery in
, offers opportunities to better understand this fungus, and presents possibilities for more detailed studies on lignocellulosic biomass degradation that may lead to future biotechnological and industrial applications.
Separate inverter-based summers for each eye are introduced into the decision feedback equalizer (DFE) of a single-ended four-level amplitude modulation (PAM-4) receiver for memory interfaces. The ...summers increase the input swing of the slicers while maintaining the advantages of inverter-based amplifiers with higher gain and lower power consumption than current-mode logic (CML) amplifiers. The high-gain summer can improve clock-to-Q delays of slicers in the PAM-4 DFE without increasing the power consumption of the slicers. This can alleviate the timing constraint that the DFE must meet to respond correctly to the previous data. The non-linear gain of the inverter-based structure can be ignored by using separate paths depending on each eye. A prototype chip was fabricated in a 65 nm CMOS process. At 24 Gb/s, the DFE can achieve a bit error rate (BER) of 10 −12 with an eye width of 100 mUI with −7.3 dB insertion loss at Nyquist frequency and the power efficiency of 0.73 pJ/b.
This brief presents a single-ended transmitter for a low-power DRAM that switches equalization modes to provide improved matching to channel impedance and reduced energy consumption. The ...transmitter's voltage-mode driver responds to the incoming data by selecting between phase equalization and current-mode amplitude equalization. The impedance matching with the channel is further improved by reducing the variation in on-resistance exhibited by the driver. A prototype chip that uses supply voltages of 0.5 V for the driver, and 1.05 V for rest of the blocks, was fabricated in a 65 nm CMOS process and occupied 0.0698 mm2. This prototype can compensate for a channel loss of 11.8 dB at a data-rate of 12 Gb/s while consuming 1.30 pJ/bit.
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