Actual industrial processes often exhibit multimodal characteristics, and their data exhibit complex features, such as being dynamic, nonlinear, multimodal, and strongly coupled. Although many ...modeling approaches for process fault monitoring have been proposed in academia, due to the complexity of industrial data, challenges remain. Based on the concept of multimodal modeling, this paper proposes a multimodal process monitoring method based on the variable-length sliding window-mean augmented Dickey-Fuller (VLSW-MADF) test and dynamic locality-preserving principal component analysis (DLPPCA). In the offline stage, considering the fluctuation characteristics of data, the trend variables of data are extracted and input into VLSW-MADF for modal identification, and different modalities are modeled separately using DLPPCA. In the online monitoring phase, the previous moment's historical modal information is fully utilized, and modal identification is performed only when necessary to reduce computational cost. Finally, the proposed method is validated to be accurate and effective for modal identification, modeling, and online monitoring of multimodal processes in TE simulation and actual plant data. The proposed method improves the fault detection rate of multimodal process fault monitoring by about 14% compared to the classical DPCA method.
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•Sulfide preferentially reduces ferrihydrite than As(V).•Fast formation of FeS effectively protects further reduction of ferrihydrite.•Formation of FeS and other Fe(II)-Fe(III) ...minerals protect As desorption.•Less than 10% As participates in kinetic desorption and re-adsorption.
This study investigated the coupled dynamics of the redox transformation of arsenic-containing ferrihydrite, and arsenate desorption and re-adsorption in presence of sulfide. Batch experiments, various microscopic and spectroscopic analyses collectively revealed that electrons from sulfide competitively transferred to ferrihydrite and no arsenate was reduced. The reductive dissolution of ferrihydrite by sulfide led to the quick formation of FeS that competitively decreased the availability of sulfide for its subsequent reduction of ferrihydrite. The quick formation of FeS was followed by a relatively slow transformation of ferrihydrite to magnetite and other Fe(II)-Fe(III) minerals that were primarily bound to the residual ferrihydrite surfaces. As a result of the preservation of As-containing ferrihydrite and surface covering by the secondary minerals, the majority (> 90%)of sorbed arsenate resided in the solid phase, and <10% of arsenate participated in the desorption process during the ferrihydrite dissolution and transformation. The desorption of arsenate was fast, and followed by the kinetic re-adsorption. The rate and extent of the re-adsorption was consistent with the dynamic transformation of the secondary minerals and their sorption affinity toward As. The results have a strong implication to understanding of As concentration changes during the redox transformation of As-containing minerals in groundwater systems.
VBSME (variable block size motion estimation) is adopted in the MPEG-4 AVC/H.264 standard. In order to increase the hardware utilization for VBSME with FSBMA (full search block matching algorithm), ...this paper proposed a new high-performance reconfigurable VLSI architecture to support "meander"-like scan format for a high data reuse of search area. The architecture can support the three data flows of the scan format through a reconfigurable computing array and a memory of the search area. The computing array can achieve 100% processing element (PE) utilization and can reuse the smaller blocks' SADs to calculate 41 motion vectors (MVs) of a 16X16 block in parallel. The design is implemented with TSMC 0.18 mum CMOS technology. Under a clock frequency of 180 MHz, the architecture allows the real-time processing of 1280 x 720 at 45 fps in a search range -16, +16.
Partially reconfigurable systems are promising computing platforms for streaming applications, which demand both hardware efficiency and reconfigurable flexibility. To realize the full potential of ...these systems, a streaming-based partially reconfigurable architecture and unified software/hardware multithreaded programming model (SPREAD) is presented in this paper. SPREAD is a reconfigurable architecture with a unified software/hardware thread interface and high throughput point-to-point streaming structure. It supports dynamic computing resource allocation, runtime software/hardware switching, and streaming-based multithreaded management at the operating system level. SPREAD is designed to provide programmers of streaming applications with a unified view of threads, allowing them to exploit thread, data, and pipeline parallelism; it enhances hardware efficiency while simplifying the development of streaming applications for partially reconfigurable systems. Experimental results targeting cryptography applications demonstrate the feasibility and superior performance of SPREAD. Moreover, the parallelized Advanced Encryption Standard (AES), Data Encryption Standard (DES), and Triple DES (3DES) hardware threads on field-programmable gate arrays show 1.61-4.59 times higher power efficiency than their implementations on state-of-the-art graphics processing units.
This brief presents a reconfigurable VLSI architecture which is designed for multi-transform codec in several video coding standards of MPEG-2/4, VC-1, H.264/AVC and AVS. The reconfigurable multiple ...constant multiplication algorithm with two fusing strategies is provided to generate constant multipliers in the matrix calculation blocks. Additionally, adder-sharing strategy is adopted in the unified preprocessing/postprocessing block to save circuit areas. The proposed architecture can support different standards through static reconfiguration and forward/inverse transform functions through dynamic reconfiguration. It is suitable for the real-time processing of 1080P HD video codec with six video standards transforms.
The 4 4 integer transforms have been adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 4 x 4 forward and inverse transforms for H.264 are deduced. A new ...dynamically reconfigurable architecture without transpose memory for the integer transforms is proposed on the ba- sis of the new SFGs. In comparison with the existing de- signs, the number of computing elements can be cut down through dynamically reconfiguration in our design. Our design is implemented with 0.18#m CMOS technology. Un- der a clock frequency of 200 MHz, this architecture allows the real-time processing of 4096x2048 at 30 fps with the area cost of 5140 gates and the power dissipation of 15.64mW.
Current FPGAs contain routing resources of diiTerent lengths and connectivity, and the connection relation of which are described by hierarchical General routing matrix (GRM). In this paper, we ...present a practical routing algorithm which can represent the complex driving relationships contained in GRMs and utilize routing resources more efficient for GRM based FPGAs. First, we build Routing resource graph (RRG) by a bottom-up way, then employ A* directed search algorithm while dynamically updating the base cost of routing resource nodes, so that the utilization rate of routing resources can be enhanced, and this routing algorithm has high-adaptabillty to latest FPGA architectures. The experiment result shows that the utilization rate of hex lines and long lines has been raised by 6%and 8% respectively.
Heterogeneity in physical and chemical properties is a common characteristic in a subsurface environment. This study investigated the effect of physico-chemical heterogeneity on arsenic (As) sorption ...and reactive transport under water extraction in a layered system with preferential flow paths. A flume experiment was performed to derive the spatio-temporal data of As reactive transport. The results indicated that the heterogeneous system significantly accelerated downward (vertical direction) As migration as a coupled effect of physical and chemical heterogeneity that led to fast As transport with low As sorption along the preferential flow paths. The results also indicated that such a heterogeneity effect was driven by water extraction that enhanced the downward groundwater flow along the preferential flow paths. Numerical simulations were performed by matching the experimental results to provide insights into the dominant processes controlling the As migration in the heterogeneous systems. The simulation results highlighted the importance of the kinetic oxidation of mineral-bonded Fe(II) to Fe(III) in the clay matrix that dynamically increased As sorption affinity and retarded As reactive transport. A coupled model of reactive transport along the preferential flow paths, sorption-retarded diffusion from the preferential flow paths into the clay matrixes, and reactions that change sorption affinity in the matrix was required to describe the As reactive transport systems with physico-chemical heterogeneities. The results have strong implications for understanding and modeling As downward migration from shallow to deep aquifers under groundwater pumping conditions in field systems with inherent heterogeneity.
Accelerating Boolean Matching Using Bloom Filter ZHANG, Chun; HU, Yu; WANG, Lingli ...
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,
2010, Volume:
E93.A, Issue:
10
Journal Article
Peer reviewed
Boolean matching is a fundamental problem in FPGA synthesis, but existing Boolean matchers are not scalable to complex PLBs (programmable logic blocks) and large circuits. This paper proposes a ...filter-based Boolean matching method, F-BM, which accelerates Boolean matching using lookup tables implemented by Bloom filters storing pre-calculated matching results. To show the effectiveness of the proposed F-BM, a post-mapping re-synthesis minimizing area which employs Boolean matching as the kernel has been implemented. Tested on a broad selection of benchmarks, the re-synthesizer using F-BM is 80X faster with 0.5% more area, compared with the one using a SAT-based Boolean matcher.
This paper presents a 16-bit coarse-grained reconfigurable computing unit. It consists of computing part and interconnection part. The computing part includes adders/subtractors, shifters and ...complementers, whereas the interconnection part includes multiplexers. Apart from basic functions, it is capable of performing 1-output and 2-output constant multiplication, 4-input adder tree, absolute difference and butterfly operation. The implementation results show that the area is 2964 gates with the critical path of 18.24ns under 130-nm CMOS technology.