In this letter, we propose a compliance test emulation method for high-speed serial links based on source and channel modeling. The source and channel are characterized by using the proposed 2-tone ...sinusoidal jitter (SJ) modeling and impulse responses, respectively. The proposed 2-tone model represents periodic jitter components which include the phase noise and power supply induced jitter (PSIJ). The proposed method enables a sink device-only compliance test by effectively emulating the source devices and channels, which reduces the test time and cost. The effectiveness of the proposed link emulation method is demonstrated by comparing its performance with that of conventional compliance tests.
This paper introduces a practical power supply design method for the display panel of smartphone. The specific goal of this design method is to reduce the voltage stress over the internal MOSFET of ...the power supply for more reliable operation. A power integrity analysis is conducted to evaluate a factor which increases the voltage stress over the internal MOSFET. Based on this analysis, two PCB layouts are designed for case studies. Reduced voltage stress is verified in the case study.
A shunt-series mixed resonant coupled structure for the wireless power transfer (WPT) applications is proposed. If the coils are designed to have proper inductance values, the power transfer ...efficiency depending on distance has proportional relation only to the shunt capacitors. It enables that the proposed structure facilitates tracking the maximum WPT efficiency according to distance. In the experiment, two pairs of resonant square coils on PCB with different turn ratio (5/10 turn) are compared for 6.78 MHz operation. Both coils have almost same maximum WPT efficiency by optimizing the series and shunt capacitors. But the 10-turn coil only demonstrates aforementioned relation. The proposed structure with 10-turn coil shows that the efficiency of 77.7 % is achieved at a distance of 30 mm.
This paper presents an analysis of a simulated serpentine signal line for a DDR3 memory interface. DDR implementation on a PCB should allow for the estimation of the figure except for the DQ length ...and impedance matching. To match the DQ timing specification in a PCB (printed circuit board), a serpentine line is simulated using an EM (electromagnetic) tool and DOE (design of experiments) analysis. In the same manner, the weight of a serpentine structure is quantified by comparing it with the other factors of PCB routing. The simulated factors prioritize the design of a memory interface in a system.
This paper introduces a practical methodology to improve power integrity performance of the chip-package-PCB systems for smart TVs. For power integrity analysis, a chip, package and PCB are modeled ...as lumped element circuits for simplicity. Case studies are presented to optimize MLCC placement using chip-package-PCB co-simulation under fixed SoC design. In case studies, CPU power net of an application processor is chosen, and voltage droop is measured as a design weight on each physical domains. The introduced methodology is evaluated through experimental verifications.
This paper presents a novel methodology for on-chip power-noise modeling in the early stage of system-on-chip (SoC) design. Conventionally, the on-chip power-noise simulation is performed in ..."placement and routing" design stage. Therefore, designers experience difficulty in applying the simulation results to improve power-noise performance because of the delivery time. The proposed methodology enables modeling of the dynamic current profile, without any geometry information and estimation of SoC power noise in the register-transfer-level design phase. Each SoC sub-block is defined as a unit simplified chip power model (SCPM), and the defined unit SCPMs are integrated into one SCPM, including multiblock characteristics. SCPM presents various types of current profiles to accurately predict the maximum current peak, and it includes the background current to prevent overestimation of the ac current. To improve the simulation accuracy, this paper proposes a voltage ripple measurement method that considers the SoC operating scenario. The simulation results of the SCPM are verified by the measurement results, and the SCPM methodology shows the correlation results of 7 and 18 mV on two test vehicles with a 1.1 V core voltage. In the chip-package design industry for electronic applications, the proposed methodology presents a design guide for the power delivery network, such as essential capacitance per location (e.g., chip, package, and printed circuit board) and the limit of the off-chip routing inductance. In addition, the forecast by the SCPM simulation shows that preactive design is available at the early stages of the design process.
The authors present a practical design process that considers the power noise problem in CPU blocks for application processors used in smart TVs. The target impedance is determined by modelling the ...RLC circuit of a system-on-chip power net. The target impedance of a power delivery network is then determined by applying the extracted chip current profile for finalising the design budget. The authors modelled the on-chip power net by combining vector network analyser measurements with an on-chip model for power integrity analysis. The authors demonstrated the optimisation and design strategy by using a ball grid array ball interconnection and case studies on the placement of multilayer ceramic capacitors. The simulation results showed good agreement with the measurement results. The error in the minimum value (negative direction) by voltage droop was less than 8.6%, while the difference in voltage noise ripple was 2.69% for a criterion of 1.1 V assuming a worst-case condition of 1.2 V.
