To analyze and compare buffer size requirements of different cache coherence policies will provide beneficial guidelines for NoC design. However, it is not an easy task, because 1)packet flows ...generated by cache coherence events do not conform to the Poisson process, traditional queue theorem can't be applied to the performance analyzing for the NoCs that support cache coherence, 2) broadcast or multicast operations, which will duplicate the cache coherence packets, makes the analysis much more complicated. To address these challenges, in this paper, we use the stochastic network calculus to analyze the backlog bounds of different cache coherence policies. Specifically, we utilize Markov-modulated On-Off (MMOO) flow to model the arrival process of cache coherence events, and then deduce the general backlog bounds for different cache coherence policies. Furthermore, to deal with packet duplication issues in broadcast or multicast operations, we develop an analytical model based on scaling functions to study their impacts on backlog bounds.
Current hardware implementations of TLS (thread-level speculation) in both Hydra and Renau's SESC simulator use a global component to check data dependence violations, e.g. L2 Cache or hardware list. ...Frequent memory accesses cause global component bottlenecks. Implementation and verification of the global component dramatically slows the processor's frequency. In this paper, we propose a cache coherence protocol using a distributed data dependence violation checking mechanism for TLS. The proposed protocol extends the current MESI cache coherence protocol by including several methods to exceed the present limits of centralized violation checking methods. In order not to broadcast every exposed write to the snooping bus, the protocol adds an invalidation vector to each private L1 cache to record threads that violate RAW data dependence. It also adds a versioning priority register that compares data versions. Added to each private L1 cache block is a snooping bit which indicates whether the thread possesses a bus snooping right for the block. The L1 Cache gets a bus snooping right when setting snooping bit. The L1 Cache catches exposed read miss whose address matching cache block address field. If a read miss from a remote core with a lower versioning priority, the L1 Cache updates the invalidation vector according to the core ID on the bus. If TLS runtime is going to commit or invalidate a thread, then L1 Cache invalidates threads whose bits have been set in the invalidation vector and changes any cache blocks to a corresponding non-speculative state. In order to implement the proposed protocol, we modified the SESC simulator, which is an open-source cycle-accurate simulator, to confirm its correctness and analyze its performance.
Several memory architectures have been proposed to enable TLS in multi-core system. Each has its own data dependence violation mechanism and speculative thread restart policy. And most of them use a ...global component to check data dependence violation. No analytical model has been proposed to compare the impact of different memory architectures on thread restarts and the global component processing delay. In this paper, we proposed analytical models for such comparison. The analytical models counts in: memory access frequency, data dependence violation checking mechanisms and thread restart policy. We derived the equation for the thread restart probability of an application & the processing delay of global components by use of probability theory and network calculus. The analytical results indicate three facts. First, the radical data dependence violation mechanism leads to much higher thread restart probability than the precise one. Second, the delayed restart policy reduces the total restarts dramatically. Third, global components will bottleneck if memory access is frequent or too many cores execute speculative threads at the same time.
In our previous investigations, we have proved that the viscoelasticity of the Articular chondrocytes undergoes dramatic changes during their normal development, however, whether the temperature, one ...of the important factors in cell cultivation and cartilage tissue engineering, is related with the viscoelasticity of cell in not known. The goal of this study was to characterize the changes of viscoelastic properties of chondrocytes in different age group under different temperature. The micropipette aspiration combined with a standard linear viscoelastic solid model was used to quantify the effect of temperature changes on viscoelastic properties and deformation recovery of chondrocytes isolated from different age groups. Results have shown that temperature significantly influences the viscoelastic properties of chondrocytes isolated from different group and the deformation recovery of which have significantly changed with temperature changing. Moreover, we found that the cytoskeletal network were more sparsely, and the contents of the components were reduced in old cells determined by immunohistochemistry, LSCM, real time PCR and western blotting compared with the adult and the young cells. These findings provide substantial temperature-related information which may be relevant for chondrocyte-based cartilage tissue engineering.
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