Recently, the VRC (virtual reconfigurable circuit) has become a mainstream solution for EHW (evolvable hardware) research. In this paper, A LUT-based VRC model is proposed, which can be applied for ...random logic function evolution. Different kinds of LUTs with appropriate interconnections were studied on a FPGA-based platform. Research were also performed in this platform to compare with the current VRC model such as VRC1 SinMan and VRC2 Sekan-ina. The results show that 3-input LUT with a direct interconnection achieves about 8% improvement in fitness value after 20,000 generations, and obtains obvious progress in logic resource utilization rate.
This paper presents a statistical method to build up interconnect timing library of static timing analysis for FPGA design. To overcome a large number of negative values in the traditional ...interconnect timing library, the statistical method is introduced. The experimental results show that the proposed method could improve the positive ratio and achieve up to 22.35% on average. Compared to the tested delay results on the FPGA chip, the delay error rate can be reduced from 13.58% to 11%.
With the emerging applications such as AI/ML, exploring the FPGA design space for the optimal performance becomes important and also challenging. The popular tool COFFE was built on an academic ...architecture and cannot be applied directly to modern FPGA chips with GRM (general routing matrix) architecture. In this work, we present our recently developed fully Automated Transistor-level Efficient and Accurate tool, AutoTEA, which features accurate area and delay models, and a fast solution space exploration method for GRM FPGA circuit optimization. The results show that AutoTEA is able to improve a previously manually optimized design (on the tape-out FPGA chip) by 11%.
Visualization software can convert circuit testing results into waveform images. In this paper a web-based waveform visualization software package is proposed by using Python as backend data parser ...and JavaScript to create lines in frontend HTML canvas images. Control of waveform is introduced with JavaScript functions. This visualization package has no dependencies on local software other than browsers, and can complete waveform depiction in 68.2ms on average by applying lazy evaluation in frontend drawing process.
Chip verification platform based on Internet or combined with cloud computing makes chip verification and test more flexible, cost-effective, and efficient. The task scheduling algorithm of the ...platform significantly determines its performance in handling the test tasks. This paper proposes an exponential dynamic weighted fair queuing(EDWFQ) algorithm for task scheduling in chip verification platform. The proposed algorithm makes the completion time of users be close to the result of SJF which is the best algorithm in minimizing the completion time. The proposed algorithm also solves the problem of starvation of SJF. The result demonstrates that EDWFQ scheduling algorithm has a lower user's Average Completion Time than FCFS, RR, RRSJF algorithm and has the capacity to solve the problem of starvation as FCFS, RR, RRSJF algorithm does. And the EDWFQ scheduling algorithm is successfully applied to the BR0101 chip verification platform.
An increasing number of high-performance computing system developed on FPGA devices need access to mass storage devices for storing data, the serial ATA protocol is widely used in the modern computer ...systems for transferring data between the host and hard disks or solid-state drives. This paper describes the design and implementation of serial ATA physical layer core based on the Xilinx GTX transceiver. With the method of cyclically changing the GTX line rate, the SATA hard disk with different line rate can be automatically identified and linked, realizing backward compatibility. An embedded system has also been developed for validating the functionality of our SATA physical layer core. We test our physical layer core with connecting our core to both SATA3 and SATA2 hard disks. The experimental result has indicated our core can not only provide the whole functionality required by the SATA physical layer, but also utilize very few logic resources on FPGA.
The scale of modern FPGAs is expanding and applications on FPGA are becoming more and more complex. Applications requiring high-density routing in large-scale FPGA determine that CAD tools not only ...require large memory consumption, but also require long routing runtime. This paper proposes a method to describe the regularity of interconnect resources in CB/SB structure, and then applies a two-level template method to store the routing resource graph (RRG) which describes the detailed FPGA interconnect resources. This algorithm fully considers the high regularity of interconnect resources in large-scale FPGAs with CB/SB structure, memory footprint could be reduced. At the same time, RRG created by this method does not affect the routing search space, thus routing runtime will not change significantly. Implementation of the algorithm on VPR platform shows a memory reduction of 1.83X could be achieved at a routing runtime penalty of 1.07X.
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