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► Electromigration lifetime of Cu interconnects with a few percent of Al or Co or Mn is increased. ► We model an incubation time or void nucleation time before void growth. ► The ...model changes the current exponent n used for lifetime extrapolation from usual n=1 to n=2. ► The model also provides an increase of activation energy of metal atoms diffusion mechanism.
This study shows that in Cu interconnects with different doping elements (e.g., Al, Co, Mn) electromigration failure times may be significantly increased because of an incubation time prior to the usual void formation. The presence of a significant incubation time provides a change from the common value of 1 to a value of 2 of the current exponent of Black’s equation, mostly used for lifetime extrapolation at use conditions. Moreover, an increase of the activation energy up to 1.4eV has been experimentally obtained. This gives additional room for reliability lifetime extension.
In this work, we present the extensive electrical characterization of 4kb Phase-Change Memory (PCM) arrays based on "Wall" structure and Ge-rich GeSbTe (GST) material, integrating a SiC dielectric ...with low thermal conductivity surrounding the heater element for enhanced cell thermal efficiency. We investigate the effects of the introduction of such dielectrics on the electrical performances of the device and we provide a promising path to achieve energy-efficient PCM cells supporting our results by electro-thermal TCAD simulations.
Using a metal-organic tungsten based precursor, a fluorine-free tungsten thin film has been obtained. The process deposition recipe includes a plasma-enhanced CVD (PECVD) step and atomic layer ...deposition (ALD) cycles. A set of physicochemical characterizations including X-ray reflectivity (XRR), in-plane X-ray diffraction (XRD), wavelength dispersive X-ray fluorescence (WDXRF), plasma profiling time of flight mass spectrometry (PPTOFMS) and microscope observations has been realized in order to study the W thin film structure and properties. The film is perfectly conformal whatever the structure size investigated (from tens of nanometers to micrometers wide). It was also highlighted that the F-free W film exhibits the lowest electrical resistivity phase (α-W) but is not pure. Indeed, in addition to a top surface oxidation, a layer located at the W film / substrate interface is present. This interface layer (IL) contains impurities, including carbon and oxygen, due to ligand decomposition. This IL might be deposited during the soak step or during the PECVD step.
The W liner with thicknesses ranging from 3 to 4nm has been implemented on PCRAM structures in order to evaluate its impact on contact plug resistivity. First electrical results are promising and demonstrate the interest of using a F-free low resistance W liner. At the aspect ratio studied, the gain in terms of contact plug resistivity is about 20% compared to the process of reference using a TiN liner. Modeling shows that this benefit is mainly due to the reduction of interface resistances.
•RESET state of Ge-rich GST is not only resistive but also shows a capacitive component.•As good as trap-assisted, granular models explain heterogeneous materials electrical behavior.•SET state is ...not simply ohmic. Characteristics resemble those of a doped semiconductor.•Overall characteristics assigned to chemical and phases heterogeneities. In relation with the tendency of the Ge-rich alloys to decompose in pure Ge and GST phases.
Ge-rich GeSbTe (GST) alloys are attracting Phase Change Materials for future memories as their higher crystallization temperature offers an extended range of applications. We have studied the electrical characteristics of PCM cells using such alloys as active layers. We show by impedance spectroscopy that the cells in the RESET (amorphous) state are not only resistive but also exhibit a capacitive component. Although trap-assisted conduction models are apparently able to describe the I(V) and I(T) characteristics of the devices in this state, their physical background is thus questionable. Alternatively, we show that granular models, describing electrical transport through conductive grains separated by insulating interfaces, are also able to simulate these characteristics, while fed by physically sound fitting parameters. Moreover, we show that the SET (crystalline) state is not simply ohmic but that its characteristics, as conductive as a metal but reacting as an insulator to temperature, resemble to those found in a semiconductor doped with a very low ionization energy defect. Finally, all these characteristics can be understood by considering that the electrical properties of cells made of Ge-rich GST layers are not those characteristic of some defective and homogeneous material but instead result from strong chemical heterogeneities found both in the amorphous and crystalline states of these Ge-rich alloys.
In this paper we explain the advantages of very thin layers (in the channel and in the BOX) of the silicon-on-nothing (SON) transistors. Electrical results are also presented, with gate length down ...to 38 nm, with a conduction channel thickness as thin as 9 and 5 nm. It is also demonstrated that SON is better suited than bulk for accepting a metallic gate for low-voltage operation due to its intrinsic low threshold voltage. We have integrated midgap CoSi
2 metal gate by total gate silicidation on SON transistors with Si-conduction channel thickness down to 5 nm. Finally, we will analyse the ITRS’01 CMOS Roadmap and show that SON allows reaching the
I
on/
I
off specifications down to the 32 nm node and approaching closely those for the 22 nm node, that is by far impossible with bulk.
Of great interest for sub-65
nm interconnect technologies, low-
k barriers are potentially sensitive to Cu diffusion and oxygen-based contamination, respectively leading to short circuits and to ...performance degradations of Cu lines. Two characterization methods were developed to evaluate these potential weaknesses, (i) liquid phase decomposition (LPD), coupled to Cu contamination analysis in a sacrificial silicon oxide layer, and (ii) nondestructive reflectivity. LPD was shown to detect defects on the Cu surface or in the barrier itself that cannot be investigated with local analysis such as SIMS probe. Results evidenced the degradation of barrier efficiency against Cu diffusion with the low-
k barrier thickness reduction. On the opposite, reflectivity measurements showed that hermeticity of these barriers to oxygen diffusion is not critical for most of the dielectric barriers with
k-value higher than 4. The two techniques developed in this study will be useful to evaluate advanced low-
k barriers.
The formation of a copper silicide interfacial layer by surface reaction in a plasma enhanced chemical vapour deposition (PECVD) system has been studied. Tri-methyl silane (TMS, SiH(CH
3)
3) has been ...employed as the Si source as an alternative to more conventional silane (SiH
4) approach. TMS precursor has been chosen due to improved control of Si penetration into the copper S. Chhun, L.G. Gosset, N. Casanova, J.F. Guillaumond, P. Dumont-Girard, X. Fedespiel, R. Pantel, V. Arnal, L. Arnaud, J. Torres, Microelectronic Engineering 76 (2004) 106–112. AFM, SIMS, light scattering, FT-IR spectroscopy and dielectric constant measurements were performed on various stacks to evaluate CuSiN formation. Resistance, leakage, and electromigration (EM) reliability characterization were performed on test structures based on 65
nm design rules. Nitridation step in silicidation process was shown to have positive impact on EM reliability, minimizing the line resistance increase.
Basic physical properties as well as electrical and reliability performance of Infusion™ processing were evaluated. This approach, proposed as an alternative to CuSiN and electrolessly deposited ...Co-alloys, was shown to join the benefits of these two techniques without well-known associated drawbacks. Indeed, it is a uniform process, acting as an efficient Cu diffusion barrier, which does not require specific integration development. Different processes were introduced in a multi-level interconnect stack using ULK/USG stack as IMD, showing excellent electrical properties, and three times electromigration time-to-failure improvement with respect to standard SiCN barrier. However, it was shown that existing process conditions lead to some introduction of N atoms into ULK dielectric, showing there is still some room for process optimization in architectures using un-capped ULKs, to keep the benefits of EM improvement and aggressive effective dielectric constant.
A new process, based on the interaction between Si and N rich gas cluster and post Cu CMP features surface, was integrated in a multi-level Cu interconnect stack using 65 nm design rules. Using the ...same integration scheme as stand-alone SiCN dielectric capping, excellent electrical properties were achieved when the process was implemented with a USG layer on top of a porous Ultra-Low K. Furthermore, 3x electromigration time to failure improvement was evidenced, making the approach very promising to address EM performance requirement for the most advanced technology nodes. Moreover, contrary to PE-CVD CuSiN approach, the process does not depend on Cu crystallographic orientation. Finally, when the implantation process is performed on un-capped ULK, a deep N contamination occurs. Therefore, the process must be optimized to preserve the interest of this technique for the most aggressive architectures.
Recently Silicon Photonics has generated an outstanding interest for integrated optical communications. In this paper we describe a 300mm Silicon Photonics platform designed for 25Gb/s and above ...applications at the three typical communication wavelengths and compatible with 3D integration. Main process features and device results are described.
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