Abstract
The scaling of transistors with thinner channel thicknesses has led to a surge in research on two-dimensional (2D) and quasi-2D semiconductors. However, modulating the threshold voltage (
V
...T
) in ultrathin transistors is challenging, as traditional doping methods are not readily applicable. In this work, we introduce a optical-thermal method, combining ultraviolet (UV) illumination and oxygen annealing, to achieve broad-range
V
T
tunability in ultrathin In
2
O
3
. This method can achieve both positive and negative
V
T
tuning and is reversible. The modulation of sheet carrier density, which corresponds to
V
T
shift, is comparable to that obtained using other doping and capacitive charging techniques in other ultrathin transistors, including 2D semiconductors. With the controllability of
V
T
, we successfully demonstrate the realization of depletion-load inverter and multi-state logic devices, as well as wafer-scale
V
T
modulation via an automated laser system, showcasing its potential for low-power circuit design and non-von Neumann computing applications.
The 2-D semiconductors have been recognized as promising channel materials for the ultimately scaled transistor technologies beyond silicon. An essential technology enabler for 2-D semiconductor ...electronics is the development of dielectric materials interfaced with 2-D semiconductors. In this review article, we overview different types of dielectric materials that are suitable for different application scenarios, including high-<inline-formula> <tex-math notation="LaTeX">{k} </tex-math></inline-formula> gate dielectrics, low-<inline-formula> <tex-math notation="LaTeX">{k} </tex-math></inline-formula> spacers, and thermal management materials under the paradigm of 2-D semiconductor electronics. A material selection guideline for dielectric materials and the key process technology modules are discussed in detail. A special emphasis is made on how each of the dielectric technologies may enable the further scaling and practical applications of 2-D semiconductor transistors. The state-of-the-art device technologies are summarized, and the remaining challenges toward practical applications are discussed from the industrial perspective.
Recent technology development of logic devices based on 2-D semiconductors such as MoS<inline-formula> <tex-math notation="LaTeX">_{\text{2}}</tex-math> </inline-formula>, WS<inline-formula> ...<tex-math notation="LaTeX">_{\text{2}}</tex-math> </inline-formula>, and WSe<inline-formula> <tex-math notation="LaTeX">_{\text{2}}</tex-math> </inline-formula> has triggered great excitement, paving the way to practical applications. Making low-resistance p-type contacts to 2-D semiconductors remains a critical challenge. The key to addressing this challenge is to find high-work function metallic materials which also introduce minimal metal-induced gap states (MIGSs) at the metal/semiconductor interface. In this work, we perform a systematic computational screening of novel metallic materials and their heterojunctions with monolayer WSe<inline-formula> <tex-math notation="LaTeX">_{\text{2}}</tex-math> </inline-formula> based on ab initio density functional theory and quantum device simulations. Two contact strategies, van der Waals (vdW) metallic contact and bulk semimetallic contact, are identified as promising solutions to achieving Schottky-barrier-free and low-contact-resistance p-type contacts for WSe<inline-formula> <tex-math notation="LaTeX">_{\text{2}}</tex-math> </inline-formula> p-type field-effect transistor (pFETs). Good candidates of p-type contact materials are found based on our screening criteria, including 1H-NbS<inline-formula> <tex-math notation="LaTeX">_{\text{2}}</tex-math> </inline-formula>, 1H-TaS<inline-formula> <tex-math notation="LaTeX">_{\text{2}}</tex-math> </inline-formula>, and 1T-TiS<inline-formula> <tex-math notation="LaTeX">_{\text{2}}</tex-math> </inline-formula> in the vdW metal category, as well as Co<inline-formula> <tex-math notation="LaTeX">_{\text{3}}</tex-math> </inline-formula>Sn<inline-formula> <tex-math notation="LaTeX">_{\text{2}}</tex-math> </inline-formula>S<inline-formula> <tex-math notation="LaTeX">_{\text{2}}</tex-math> </inline-formula> and TaP in the bulk semimetal category. Simulations of these new p-type contact materials suggest reduced MIGS, less Fermi-level pinning effect, negligible Schottky barrier height and small contact resistance (down to 20 <inline-formula> <tex-math notation="LaTeX">\Omega \mu </tex-math> </inline-formula>m).
Recent technology development of logic devices based on 2-D semiconductors such as MoS2, WS2, and WSe2 has triggered great excitement, paving the way to practical applications. Making low-resistance ...p-type contacts to 2-D semiconductors remains a critical challenge. The key to addressing this challenge is to find high-work function metallic materials which also introduce minimal metal-induced gap states (MIGSs) at the metal/semiconductor interface. In this work, we perform a systematic computational screening of novel metallic materials and their heterojunctions with monolayer WSe2 based on ab initio density functional theory and quantum device simulations. Two contact strategies, van der Waals (vdW) metallic contact and bulk semimetallic contact, are identified as promising solutions to achieving Schottky-barrier-free and low-contact-resistance p-type contacts for WSe2 p-type field-effect transistor (pFETs). Good candidates of p-type contact materials are found based on our screening criteria, including 1H-NbS2, 1H-TaS2, and 1T-TiS2 in the vdW metal category, as well as Co3Sn2S2 and TaP in the bulk semimetal category. Simulations of these new p-type contact materials suggest reduced MIGS, less Fermi-level pinning effect, negligible Schottky barrier height and small contact resistance (down to Formula Omitted).
A write-enhanced single-ended 11T complementary FET (CFET) SRAM capable of performing reconfigurable compute-in-memory (CIM) using a single bitcell is presented for the first time. By leveraging the ...dummy PFETs within the standard 6T (or 8T) CFET SRAM layout, the write ability of the proposed 11T SRAM can be enhanced more than 2.5 times compared with the 6T (or 8T) SRAM without sacrificing the write half-selected disturb. In addition, the dummy PFETs acting as additional write transistors offers an opportunity to perform Boolean CIM with three reconfigurable schemes introduced in this work. By employing the CFET technology, the 11T CFET SRAM cell shows tiny area overhead compared with the 6T high current SRAM cell (HCC) using non-stacked CMOS and has a comparable footprint as the standard 8T CFET SRAM cell.
Heat spreading is critical in reducing the overall junction temperature of monolithic system-on-chips (SoCs) and high-heat-flux radio frequency (RF) applications. Bulk diamond has the highest thermal ...conductivity (TC) in nature, but its TC degrades due to the presence of smaller and highly columnar grains. Diamond thin films can be used as the back-end-of-line (BEOL) dielectrics and thermal vias for effective heat spreading if high-quality isotropic diamond growth processes are developed. In this study, we grow large-grain thin-film diamonds (0.3–25 μm) with isotropic TC (300–1,800 W/m/K). This is achieved by controlling the lateral growth and terminating smaller grains at the nucleation stage without physically damaging the substrate. The enhancement of TC is achieved by lowering grain boundary density and graphite at the grains. Thermal modeling indicates that incorporating isotropic thin diamond reduces the temperature in a realistic flip chip and a monolithic 3D deep neural net accelerator by 20% and 50%, respectively.
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•Thin-film diamonds with isotropic thermal conductivities•Thermal conductivities equal to 10× thicker conventional diamonds•Enhanced heat dissipation for system on chips, boosting reliability•Reduced temperature of 3D deep neural net accelerators by >50
Diamond-based heat spreaders can dissipate heat away from the semiconductor devices and reduce the need for energy-intensive cooling solutions such as lossy fans or sophisticated liquid-cooling systems. Malakoutian et al. develop high thermally conductive diamond thin films that enhance cooling efficiency from the hotspot to the heat sink.
The implementation of ultralow dielectric constant (k value ≈ 2) materials to reduce signal propagation delay in advanced electronic devices represents a critical challenge in next generations of ...microelectronics technologies. The introduction of well‐stacked and low polarity molecules that do not compromise film density may lead to improvements and desirable material engineering, as conventional porous SiOx derivatives exhibit detrimental degradation of thermo‐mechanical properties when their k values are further scaled down. This work presents a systematic engineering approach for controlling ultralow‐k amorphous boron nitride (aBN) deposition on 300 mm Si platforms. The results indicate that aBN grown from borazine precursor exhibits ultralow dielectric constant ≈2, high density, excellent mechanical strength, and extended thermodynamic stability. Unintentional boron ion doping during plasma dissociation that may induce artificial reductions of k value on n‐type substrates is alleviated by employing a remote microwave plasma process. Moreover, the adoption of low growth rate processes for ultralow‐k aBN deposition is found to be critical to provide for the superior mechanical strength and high density, and is attributed to the formation of hexagonal ring stacking frameworks. These results pave the way and offer engineering solutions for new ultralow‐k material introduction into future semiconductor manufacturing applications.
300 mm wafer‐scale amorphous boron nitride with ultralow dielectric constant close to 2, preserving high density of 2.1 g cm–3, and superior Young's modulus > 50 GPa is demonstrated by novel borazine‐based growth approach. Energetically favorable B‐N hexagonal ring stacking framework under low growth rate scenario is also presented.
Thesis (Ph. D.)--University of Wisconsin--Madison, 2004.
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