The aim of this work is to investigate the thermal stability of remote phosphor plates to be used in solid-state lighting systems, for the conversion of the blue light emitted by GaN-based LEDs into ...white light. A preliminary thermal characterization revealed that in normal conditions of blue light irradiance the phosphor plates can reach temperature levels higher than 60°C, which can affect both performance and reliability. The results of accelerated thermal stress tests indicate that high temperature levels can trigger a relevant degradation mechanism (estimated activation energy is 1.2eV), that drastically reduces the phosphor conversion efficiency and modifies the photometric and colorimetric characteristics of the emitted white light.
•This paper introduces the new NanoElectronics Roadmap for Europe covering topics from Nanodevices beyond CMOS and Innovative Materials to system Integration. It has been worked by the European CSA ...project NEREID which has been funded by the European Union’s Horizon 2020 research and innovation programme under grant agreement No 685559.•The NEREID roadmap gives a projection of the evolution of many Figures of Merit (FoMs) vs time for covering the most promising technologies including novel functionalities.•The NEREID roadmap delivers an understanding of the dependencies between short/ medium term (e.g. More Moore and More than Moore) and long/very long term (e.g. Beyond CMOS) activities.•The NEREID roadmap is based on a strong interaction between application and technology experts, coming from leading research players in industry and academia, especially by face to face exchange during many Workshops.•The NEREID roadmap is created in a combination of a top-down approach, which is application driven, and a bottom-up one, based on planned technology evolution to prompt new ideas for disruptive products and applications.
The NEREID project (“NanoElectronics Roadmap for Europe: Identification and Dissemination”) is dedicated to mapping the future of European Nanoelectronics. NEREID’s objective is to develop a medium and long term roadmap for the European nanoelectronics industry, starting from the needs of applications to address societal challenges and leveraging the strengths of the European eco-system. The roadmap will also identify promising novel nanoelectronic technologies, based on the advanced concepts developed by Research Centres and Universities, as well as identification of potential bottlenecks along the innovation (value) chain. Industry applications include Energy, Automotive, Medical/Life Science, Security, loT, Mobile Convergence and Digital Manufacturing. The NEREID roadmap covers Advanced Logic and Connectivity, Functional Diversification (Smart Sensors, Smart Energy and Energy for Autonomous Systems), Beyond-CMOS, Heterogeneous Integration and System Design as well as Equipment, Materials and Manufacturing Science. This article gives an overview of the roadmap’s structure and content.
In this letter, the effects of dc stress on GaN high-electron-mobility transistors' performance are investigated by means of experimental measurements and numerical simulation. A degradation of both ...dynamic (pulsed I - V ) and static characteristics (dc) has been observed on stressed devices, and it has been experimentally related to the formation of an electron trap in the AlGaN barrier layer. Numerical simulations carried out on the tested structure by introducing a trapping region at the gate edge of the device barrier confirm the experimentally observed device degradation. The worsening of the dynamic performance is induced by both an increase in trap concentration and/or depth of the trapping region while the degradation of the dc characteristics can be explained by an increase in the trapping-region depth.
We investigate the potential distribution and breakdown of GaN-on-silicon HEMTs by using a test structure with a floating sense node located between gate and drain, in the access region. To ...demonstrate the effectiveness of the adopted method, we analyze two different wafers, having different 2DEG retraction in the OFF-state and different time to breakdown. We demonstrate that: 1) the floating node can effectively be used to evaluate the potential distribution in the access region; 2-D simulations are compared with the experimental data to demonstrate the effectiveness of the method and 2) the time to breakdown is strongly influenced by the distribution of the potential (and of the electric field) in the access region. A superior robustness is found on devices characterized by an improved distribution of the 2DEG potential between gate and drain. In contrast, devices with a lesser 2DEG retraction show early breakdown when subjected to OFF-state stress. For the first time, we demonstrate a direct correlation between the 2DEG retraction and the OFF-state long-term stability of GaN-on-Si HEMTs. The results reported within this paper provide further insight on the physical origin of time-dependent breakdown in GaN-based power transistors.
Reverse-bias testing in AlGaN/GaN HEMTs at high (negative) gate voltage is found to induce a catastrophic increase in gate leakage current I G , with only a slight degradation of drain current I D . ...Electroluminescence (EL) microscopy demonstrates that leakage current injection is localized within ldquohot spotsrdquo at the gate edges, possibly corresponding to defects in the semiconductor material or at the metal-semiconductor interface. The density of ldquohot spotsrdquo increases during tests and is correlated with the increase of I G and electroluminescence intensity and with an enhancement of trapping effects such as current collapse.
A strong positive correlation between dynamic Ron and the ionization of buffer traps by injection of electrons from the Si substrate is presented. By exploring different Carbon doping profiles in the ...epi layers, the substrate buffer leakage is substantially reduced, which in turns results in lower dynamic Ron. The traps in the epi structure are characterized by different electrical techniques such as drain current transient, on-the-fly trapping and ramped back-gating experiments.
Temperature dependent DC and double pulse measurements are performed on p-GaN gated AlGaN/GaN enhancement mode power transistors. Devices with improved Schottky metal/p-GaN interface quality and ...p-GaN sidewall passivation are studied. It is shown that both processes reduce the reverse and forward gate leakage current significantly. This is related to the improved p-GaN sidewall roughness and density of interface states, all contributing to sidewall leakage. Under double pulsed testing, an untreated device shows a negative threshold voltage shift at high forward gate voltage, which is explained by hole trapping in the barrier. Improving the p-GaN sidewall quality reduces the supply of holes towards the p-GaN/AlGaN interface, and a positive threshold voltage shift is observed. This can be explained by electron injection from the channel into the barrier.
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•We provide give an overview on the most common degradation processes of GaN-based HEMTs.•We describe the time-dependence of gate degradation mechanism during off-state tests.•The ...influence of the reverse voltage as degradation accelerating factor is also provided.•We present a combined electrical, thermal and EL analysis of hot electrons degradation.•We define a methodology for the evaluation hot electrons effects.
This paper describes a deep investigation of the degradation mechanisms induced by off-state and on-state stress in AlGaN/GaN HEMTs. Concerning reverse-bias degradation, results underline that the exposure to reverse-bias stress can induce (i) a recoverable change in the gate current due to the accumulation of negative charges under the gate, (ii) and a permanent degradation of gate characteristics due to the generation of vertical parasitic leakage paths through the AlGaN layer. Further analysis of the kinetics of this degradation mechanism, correlated with time-resolved Electroluminescence (EL) measurements, allowed to define a model that explains the time-dependence of the phenomenon and the role of gate voltage as accelerating factor, providing an interpretation for both recoverable and permanent modifications of the main device characteristics induced by reverse-bias stress.
On the other hand, on devices that have shown an improved robustness against the reverse-bias gate degradation, we investigated the origin of the degradation under on-state stress. In this case, results obtained with a combined electrical and optical analysis, showed that on-state stress may induce a significant decrease in drain saturation current and Electroluminescence (EL) signal, with a degradation rate that strongly depends on the EL intensity measured before stress, which is representative of the presence of hot-electrons in the channel. On-state degradation can be ascribed to a decrease in the electric-field, due to the trapping of electrons within the barrier or at the surface induced by hot-electrons. Therefore, by using the EL signal as measure of the stress accelerating factor, it was possible to derive an acceleration law for hot-electron degradation on GaN HEMTs.
This paper reports on an extensive analysis of the breakdown of GaN-based Schottky-gated HEMTs submitted to high-voltage stress. The analysis was carried out on transistors with different lengths of ...the drain-side gatehead (L GH ), corresponding to different levels of electric field across the SiN passivation. Based on dc measurements, 2-D simulations, and optical analysis, we demonstrate the following original results: 1) when submitted to high drain voltages (in the OFF-state ), the transistors can show catastrophic failure; 2) electroluminescence microscopy indicates the presence of hot-spots on the drain-side of the gate; 2-D simulations support the hypothesis that failure occurs in correspondence of the gate-head, on the drainside edge, where the electric field in the silicon nitride passivation has its maximum; 3) this hypothesis is confirmed by the results of transmission electron microscope failure analysis that demonstrate the generation of a leakage path between the gate metal and the channel, 4) and by the dependence of the destructive voltage on the L GH value. 5) in addition, we propose and demonstrate an approach for improving the reliability of the devices, i.e., using a graded SiN passivation with increased thickness. The results described in this paper provide important information for the device optimization of Schottky-gated HEMTs.
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