Due to the scaling down, the contribution of interconnects should become preponderant for the performance of IC. The use of low-
k dielectrics and/or low resistivity metals in order to decrease the ...parasitic capacitance of interconnect is a technological requirement. Especially the use of copper, with mineral dielectric as IMD, instead of aluminium alloy is now commonly accepted. In this paper we compare the intrinsic performance of two damascene architectures. The planarization by metal CMP, which will determine the final metal thickness, may induce killer defects (shorts between lines) or degraded metal sheet resistance uniformity for multi-level metallization devices. The impact on electromigration of the damascene structure is presented: due to the reverse architecture, the grain sizes and orientations are found to be linewidth dependent. On the other hand, the life times extrapolated with different copper and barrier deposition processes vary on a large range: from similar to those obtained with aluminium for a full CVD metallization (barrier+copper) to more than one order of magnitude higher for a CVD barrier and a mixed CVD+PVD copper deposition.
We present the fabrication and characterization of ultra thin and relatively thick SiGe-On-Insulator wafers with different Ge contents prepared by Ge condensation technique. The fabrication ...procedures as well as the structural analysis are detailed. The electrical properties of advanced strained SiGe-On-Insulator (SGOI) and relaxed Germanium-On-Insulator (GeOI) wafers were investigated using the Pseudo-MOSFET method and then compared with Silicon-On-Insulator (SOI) and strained Silicon-On-Insulator (sSOI) structures. GeOI wafers with 10-nm and 100-nm film thickness show exceptionally high hole mobility as compared to both SOI and sSOI structures. The hole mobility can reach 400
cm
2/V
s. It is found that the mobilities for holes and electrons vary in opposite directions as the Ge fraction is increased. The Ge content also impacts the threshold and flat-band voltages.
300mm ultrathin Silicon-On-Insulator (SOI) wafers with SiGe/Si stacks on top were used as pre-structures for the fabrication of 5nm thick SiGe-On-Insulator (SGOI) substrates obtained by the Ge ...enrichment technique. Those substrates will be used as the channel of advanced Fully Depleted (FD) p-type Metal Oxide Semiconductor Field Effect Transistors (pMOSFET). We present in the first part the successful fabrication of 5nm SGOI wafers. Various characterization techniques are used to investigate the Ge profile and the final strain in the fabricated 5nm Si0.7Ge0.3 film. Secondary Ions Mass Spectrometry (SIMS) and Scanning Transmission Electron Microscopy (STEM) clearly show that the Ge content is very homogeneous (xGe=30±1%) in the SiGe layer. Raman spectroscopy and High Angle Annular Dark Field (HAADF) STEM both confirm that the 5nm thick SiGe film is compressively strained (−2GPa). The second part is dedicated to the sensitivity of the Ge enrichment process (based on numerical modelling). We investigate the impact of single and combined fluctuations of the pre-structure parameters (TSi, TSiGe,0, xGe,0) on the final SiGe layer (TSiGe, xGe).
Thanks to bonding, metal-gate etching without any out-of-gate Si consumption, and self-aligned transfer of alignment marks, we have processed the first 10-nm-gate-length DG MOS transistors with metal ...gates. These devices exhibit excellent short-channel effects control and high-performance characteristics. Their saturation current is very sensitive to the access resistance increase caused by film thinning required to respect the scaling rules. Moreover, their electrical properties can be tuned between LSTP and HP by independently biasing the two gates.
Complementary characterisation protocols are needed to analyse high-k insulator behaviour from DC to microwave frequencies. The extraction of Plasma Enhanced Atomic Layer Deposition HfO2 and ZrO2 ...complex permittivity was performed up to 5 GHz using dedicated test vehicles, allowing in-situ characterisation as a function of dielectric thickness. The measurement procedure was thus validated, highlighting the potential of these two dielectric materials to cover a wide range of frequencies.
We investigate in this work an original contact architecture to address 64 nm pitch transistor technology. This architecture, studied here in the fully-depleted silicon-on insulator (FDSOI) flavour, ...remains suitable for planar and 3D (trigate, FinFET) approaches. It includes a recessed gate-first process and self-aligned contacts that offer alternative solutions to technological problems such as limits in lithography resolution and stepper misalignment. Because this type of contact architecture is likely to increase parasitic coupling between gate and source/drain (S/D) contacts, a set of optimization rules is proposed based on numerical simulations. It is found that reducing gate thickness remains the best option to decrease the parasitic gate-to-S/D contact capacitance when transistors feature standard nitride spacers. The use of a low permittivity and thick gate capping layer is highly recommended to limit the sensitivity of parasitic capacitances to non-uniformity associated to chemical mechanical polishing (CMP) and stepper misalignment during S/D contacts lithography. When low-k spacers are considered, the same optimization rules are still relevant to further decrease parasitic capacitances at the transistor level. In the particular case of airgap spacers, they result in a 50% reduction of the total parasitic capacitance. Nevertheless, when used alone, low-k spacers can reduce parasitic coupling by up to 80%; they appear as a first order parameter to tune parasitic capacitances. At the circuit scale, it is demonstrated that an optimized architecture including low-k spacers is mandatory to meet the specific 10 nm node speed requirements at the circuit level. Insights are finally given to correctly choose the active area width W and supply voltage V sub(DD) taking into consideration the speed/power consumption trade-off. We particularly showed that if a voltage value lower than the nominal supply voltage is used, spacers optimization become even more effective to reach higher circuit speed at constant dynamic power consumption.
After germanium oxidation 12nm Ni has been deposited on Geo2. Sims shows that reaction started during metal deposition between metal and oxide. Then nickel reacted with germanium during RTP annealing ...forming final phase NiGe while the ceramic NixGeyOz was rejected toward the surface as observed on SEM picture. Display omitted
► Controlled of germanium oxidation process. ► Solid state reaction between nickel metal and germanium through an oxide layer. ► Reaction of Ni film with germanium oxide at room temperature forming NiGe. ► Ni diffusion through NiO metal oxide and/or Ni2GeO4 germinate layers.
Germanium based devices are of interest due to their performance potential. The use of germanium as source and drain requires low resistance access achieved by the formation of germanide (metal-germanium compound). The nickel mono-germanide (NiGe) is claimed to be the best candidate since it presents suitable electrical and thermo-kinetic qualities. However, since the germanium oxidizes instantaneously in air, we provide in this paper a study of reactions between a nanometric Ni film and a germanium (001) substrate in the presence of a native or controlled grown germanium oxide. The goal is to study the influence of the germanium oxide onto germanidation process. We report that whatever the germanium oxide types (native or grown) formation of nickel germanides can occur unlike to silica which inhibits metal/silicon reactions. Numerous characterizations such as XRD, TEM, EFTEM, SIMS and SEM lead us to propose a model. Whatever the oxide type as thick as 8nm, nickel reacts with GeO2 during its deposition and transforms into a continuous germanate layer allowing NiGe nucleation on Ge substrate. After heat treatment the entire pure Ni film has reacted while the germanate NixOyGez were present. This means that Ni transport occurred even through germanate. Finally, this NixOyGez film shifted toward the surface as a discontinued layer.
We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic V T -variability performances are obtained (A VT ...=1.45mV.μm). This leads to 6T-SRAM cells with good characteristics down to V DD =0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σ SNM <;SNM/6) down to V DD =0.7V. We also demonstrate ultra-low leakage (<;0.5pA/μm) on UT2B devices at L G =30nm by source/back biasing thanks to a low gate current and Gate Induced Drain Lowering (GIDL).
In this letter, we report the fabrication and characterization of self-aligned double-gate MOSFETs with gate length down to 6 nm. Based on molecular bonding, the interest of this original process ...relies on the fact that, for the first time, technological options such as planar process, independently biasable gates, and metallic source and drain are integrated all together to address critical issues for sub-22-nm node, such as variability, short channel effect control, and access resistance decrease. Good electrical performance of pMOS transistors is demonstrated. Short channel effects are very well controlled down to 30 nm. The independent biasing of the two gates allows tuning of the characteristics, depending on the targeted applications.
