Cascade, single and multi-bit, /spl Sigma//spl Delta/ architectures provide stable, high order quantization noise shaping used in high resolution A/D conversion. One major disadvantage of cascaded .../spl Sigma//spl Delta/ topologies is the extreme SNDR sensitivity to gain mismatch between the analog modulator and the digital error correction logic. This paper will investigate this SNDR sensitivity phenomenon for a 6th order, 1-bit quantizer and 4th order, 5-bit quantizer cascaded /spl Sigma//spl Delta/ A/D system. Circuit parameters of the switched capacitor integrator such as amplifier open loop gain, integrator gain, and amplifier offsets and layout parasitics are characterized.
14-bit, 2.2MS/s sigma delta ADCs Morizio, J.; Hoke, M.; Kocak, T. ...
Proceedings of the 25th European Solid-State Circuits Conference,
1999
Conference Proceeding
This paper presents the design and test results of a 4th and 6th order, 14-bit, 2.2MS/s sigma-delta ADC. The analog modulator and digital decimator sections were implemented in a .35µM CMOS, double ...poly, triple level metal 3.3v process. The design objectives for these ADCs was to achieve 85dB SNDR with less than 200mW power dissipation.
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