This article aims to provide deep insight into the physics of substrates for RF applications under large-amplitude signal excitations. The impact of physical parameters on substrate-induced harmonic ...distortion is modeled and well understood, from a theoretical and quantitative standpoint. This article formulates the interplay between applied voltage signal (dc or RF), interface fixed charge, and trapped charge in a charge-balance analysis for high-resistivity and trap-rich (TR) substrates. A TCAD approach gives strong insight into the impact of such semiconductor material and interface properties on the RF substrate's effective resistivity and linearity. First, a static analysis reveals how TR interface passivation overcomes the parasitic surface conduction effect using the concept of deep Fermi-level pinning. Next, substrates are analyzed in response to dynamic excitation signals. Using step functions to pulse an MOS structure from strong negative to strong positive applied charge sheds light on carrier dynamics. The characteristic time constants associated with variations in trap occupancy and in free carrier densities are discussed. Finally, sinusoidal large-amplitude signals are considered to analyze harmonic distortion from several types of substrates at various RF frequencies.
This article presents the accurate modeling results of the nonlinear behavior of a wide range of silicon-based substrates at RF. The TCAD-based model includes carrier inertia effects and captures the ...transient nonequilibrium phenomena in the semiconductor substrate regions in response to a large-amplitude RF signal. The model is applied to coplanar waveguide (CPW) lines measured on 19 different silicon-based samples that have key differences in their material and interface parameters, such as different values for nominal doping, interface oxide charge, the presence or not of a trap-rich passivation layer, and characteristic dimensions. Furthermore, the CPW line's distortion levels are measured from 25 °C up to 175 °C and at five fundamental frequencies under large-signal excitation from 50 MHz to 5.4 GHz. An excellent model to experiment correlation is achieved under all of these conditions, and the impact of the material and excitation parameters are discussed with strong physical insight provided by the simulation tool.
A novel method for increasing the effective resistivity in low-doped silicon substrates is presented. By creating a chain series of p-n depletion junctions beneath the insulator, the parasitic ...surface conduction channel is interrupted, significantly lowering substrate losses and reducing harmonic distortion in the simulated and measured CPW lines achieving performance close to the widely used trap-rich silicon substrate at RF frequencies.
This paper proposes an original approach to separately characterize self-heating and substrate effects in Fully-Depleted Silicon-on-Insulator (FD-SOI) devices. As both dynamic self-heating and drain ...to source coupling through the back-gate and substrate of an FD-SOI MOSFET induce a frequency transition in the Y-parameters in a common frequency range, it is crucial to properly separate them for further modeling. The proposed novel method is based on the extraction of the back-gate and substrate networks from the S-parameters measured at the zero-temperature coefficient bias. It enables the accurate and unambiguous extraction of thermal impedance for different biases, thus providing the extraction of the device thermal resistance and capacitance for different power levels from S-parameters measurements.
Blue, pink, and yellow colorations appear from twisted bi‐layer graphene (tBLG) when transferred to a SiO2/Si substrate (SiO2 = 100 nm‐thick). Raman and electron microscope studies reveal that these ...colorations appear for twist angles in the 9–15° range. Optical contrast simulations confirm that the observed colorations are related to the angle‐dependent electronic properties of tBLG combined with the reflection that results from the layered structure tBLG/100 nm‐thick SiO2/Si.
Fracture mechanics has been applied for more than two decades to various configurations of cracks in films on substrate. Fracture toughness data are indeed needed for the design and integrity ...assessment of many coatings and microelectronics devices. Nevertheless, it is sometimes complicated to deconvolute the constraint exerted by the substrate on the cracking process especially in the presence of viscoelastic or plastic dissipation. Here, a new on chip test method has been developed to determine the fracture toughness of freestanding submicron films. Beside the advantage of avoiding the constraint induced by the substrate, freestanding films allow, if sufficiently thin, direct observation of the fracture mechanisms by transmission electron microscopy. The design of this new nano(micro)-testing consists of two long actuator beams undergoing large internal stress. A specimen is attached to these two actuators, incorporating a notch produced by lithography. Two types of geometries are addressed, one being a double cantilever beam type configuration, while the other is a center cracked panel. Both actuators and specimen are deposited on a sacrificial layer. The etching of the sacrificial layer induces the release of the test structure, with the actuators then contracting and pulling on the test specimen. A crack is initiated from the notch tip, propagates and finally stops when the energy release rate has decreased down to its critical value. This crack arrest measurement avoids the problem of introducing a sufficiently sharp precrack. Analytical equations that describe the stress intensity factor as a function of the geometrical characteristics of the test structures are worked out to guide the dimensional analysis. Extensive finite element analysis provides the full parameter variations necessary to quantify the fracture toughness from experimental data and to capture the process of initiation, unstable cracking and arrest followed by possible further stable propagation. For the sake of a proof of concept, ∼50 and ∼100 nm-thick silicon nitride films produced by low pressure chemical vapor deposition were tested, leading to a mean fracture toughness equal to ∼2 MPam.
Multiple-gate devices, such as the planar double-gate (DG), triple-gate (TG), FinFET, Pi-Gate (PG), and Omega-Gate Silicon-on-Insulator (SOI) MOSFETs are potential candidates for achieving the ...performance targets of the International Roadmap of the Semiconductor Industry Association. In this paper, wideband experimental and three-dimensional simulation analyses have been carried out to compare the analog/RF performance of DG, TG/FinFET, PG, and single-gate (SG) SOI MOSFETs. The characteristics of the multiple-gate devices were analyzed in the dc and ac regimes from subthreshold region to strong inversion and saturation regions. In both regimes, the advantages and limitations of the multiple-gate devices over the SG structure are discussed for channel length scaling well below 100 nm. To the authors' knowledge, it is the first time that such extensive results and analyses are presented on the potential of these novel devices for high-frequency analog applications.
Graphene coatings reduce surface adhesion owing to a low surface energy. In the present work, a single CVD-grown graphene layer on Cu is shown to modify the elastic contact behavior by eliminating ...adhesion. Nanoindentation load-displacement curves exhibit higher load bearing capacity for Cu/graphene in the elastic regime compared to bare Cu and a closer agreement with Hertz law. Molecular dynamics simulations confirm the quasi-absence of adhesion between graphene and indentor tip. These results open new opportunities regarding tribological issues related to coatings or MEMS applications.
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► GP introduction has only marginal effect on UTBB MOSFET analog FoM (slightly higher body factor in devices with GP).► ADG (i.e. front- to back-gate shorten) allows improved gate-to-channel coupling ...and SCE control (DIBL, S, VTh roll-off).► ADG bring about 20% improvement of analog FoM (such as gm, Id and intrinsic gain) in short-channel UTBB MOSFETs with GP.► Simulations predict that improvements of analog FoM provided by ADG are assured in the whole dynamic operation range.► ADG allows elimination of the high-frequency substrate coupling effect, thus improving intrinsic gain at high frequency.
In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Based on experimental devices, both n- and p-type GP configurations are considered and compared with standard no-GP substrates. In a standard single-gate (SG) regime, the effect of GP implementation on analog FoM (related to slightly higher body factor and improved gate-to-channel coupling) is negligible. Moreover, p-GP implementation allows higher intrinsic gain at high frequency compared with no-GP and n-GP substrates. Furthermore, we demonstrate that application of an asymmetric double-gate (ADG) (i.e. front-gate to back-gate/substrate connection) regime allows better control of short-channel effects in terms of drain induced barrier lowering, subthreshold slope and threshold voltage control, due to improved gate(s)-to-channel coupling. Application of an ADG mode is shown to enhance analog FoM such as transconductance, drive current and intrinsic gain of UTBB SOI MOSFETs. Finally, simulations predict that improvements of analog FoM provided by ADG mode can be obtained in the whole dynamic operation range. Moreover, ADG mode provides elimination of the high-frequency substrate coupling effects.
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