We report a detailed comparison of low and high-Vd transport between various substrate- and process-induced strained MOSFETs down to 40nm gate lengths. Thanks to an original extraction method and low ...temperature measurements, we demonstrate that the mobility behaviour is deeply impacted by the down-scaling because of Coulomb scattering. Introducing this behaviour into a saturation current model, we clearly explain the I/sub ON/ enhancement trend of all strained devices.
In this work, 3D monolithic cells have been demonstrated, featuring the first perfectly crystalline upper active layer thanks to wafer bonding. The low temperature process (<600degC) of the top GeOI ...and SOI MOSFETs leads to well behaved characteristics and allows preservation of bottom FETs performance. The benefit of the decreased process temperature is highlighted by improved short channel effect control down to L G = 50 nm. Both gains in density and performance have been studied with advanced design rules. Processing CMOS on each layer leads to an average 40% density improvement as compared to 2D standard layout.
The feasibility of split capacitance-voltage (C-V) measurements in sub-0.1 mum Si MOSFETs is demonstrated. Based on the split C-V measurements, an improved methodology to extract accurately the ...effective channel length and the effective mobility is proposed. Unlike conventional I/d/(V/g/)-based extraction techniques, this new approach does not assume the invariance of the effective mobility with gate length (assumption proved to be false in this paper). This method is relevant to study transport limitations in ultimate MOSFETs as illustrated with the study of pocket implant influence on 50-nm p-MOSFETs.
We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred ...using the Smart CutTM process to fabricate 200mm GeOI wafers with Ge thickness down to 60–80nm. A full Si MOS compatible pMOSFET process was implemented with HfO2/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (ION, IOFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μh∼250cm2/V/s, ION=436μA/μm for LG=105nm), and OFF current densities comparable or better than those reported in the literature.
In this work, an optimized method to extract GIDL parameters has been used to characterize junction quality in FDSOI devices. This paper gives a practical methodology to properly apply this method: ...first, it insists on the importance to discriminate the respective contributions of GIDL and gate tunneling in drain current. Then, an activation energy criterion is used to determine the bias conditions that are appropriate to correct application of this method. Experimental values of "tunneling" field and tunneling parameter are extracted, with better reliability than with previous methods. Reliable extractions of the GIDL parameters enable to characterize junction quality independently of junction abruptness and of the impact of traps in the bandgap. This method is successfully applied and results are in agreement with expected results.
