Low-temperature (≤300°C) formation of orientation-controlled large-grain (≥10μm) Ge-rich (≥50%) SiGe crystals on insulator are realized by the gold-induced layer-exchange technique. Stacked ...structures of a-Si1−xGex (0≤x≤1)/Au/SiO2 are employed as starting materials. Here, thin-Al2O3 layers are introduced as diffusion barrier at a-SiGe/Au interfaces to suppress random bulk-nucleation and make (111)-oriented interface-nucleation on SiO2 dominant. For samples with Ge fraction of 80%–100%, (111)-oriented large-grains (≥10μm) are obtained through layer-exchange during annealing at 250°C. On the other hand, layer-exchange for Ge fraction of 50% does not proceed at 250°C. This phenomenon is attributed to retardation of lateral growth by introduction of Si. To enhance lateral growth, increase of annealing temperature is examined. As a result, (111)-oriented large-grains (≥10μm) are realized for SiGe with Ge fraction of 50%–100%, having uniform composition profiles, by annealing at 300°C. This technique is very useful to realize high-performance flexible electronics, employing plastic substrates (softening temperature: ~350°C).
•Gold-induced crystallization is developed to Ge-rich SiGe on insulator.•Layer-exchange crystallization proceeds at low temperatures (≤300°C).•(111)-oriented large-grain (≥10μm) SiGe is realized for Ge fraction of 50%–100%.
In rapid-melting-crystallization of network Ge-on-insulator (GOI), coalescence of growth-fronts inevitably occurs. To clarify crystallinity of the coalesced regions of two growth-fronts in GOI ...stripes, scanning electron microscopy and transmission electron microscopy analyses are performed. These analyses reveal that lattice planes of two growth-fronts coherently align without strains for short growth-distance (≤5μm). The lattice planes at growth-fronts start to tilt gradually for growth-distance above 5μm. For intermediate growth-distance (5–150μm), slightly-tilting lattice-planes coherently align without generating any defects, where locally-distributed strains are induced in the coalesced regions. On the other hand, for long growth-distance (≥150μm), grain-boundaries are generated in coalesced regions, and the locally-distributed strains are relaxed. The coherent lattice-alignment for growth-distance below 150μm is attributed to atomic reordering in the coalesced regions, where coalescence occurs at high temperatures around the solidification point of Ge.
•Coalesced regions of growth-fronts in melting-grown Ge-on-insulator are investigated.•Lattice planes of growth-fronts coherently align.•The coherent alignment is attributed to atomic reordering in coalesced regions.•Here, coalescence occurs at high temperatures around solidification point of Ge.•This high-quality demonstrates significant advantage of melting growth.
High-quality Ge-on-insulator (GOI) structures are essential to realize next-generation large-scale integrated circuits, where GOI is employed as active layers of functional devices, as well as buffer ...layers for epitaxial growth of functional materials. In line with this, in-depth analysis of crystallinity of rapid-melting-grown GOI is performed. Structural and electrical measurements combined with a thinning technique reveal that the crystallinity of GOI (500nm thickness) is very high and uniform in-depth direction, where high hole mobility (~1000cm2/Vs) is achieved throughout the grown layers. These findings open up a possibility of application of rapid-melting-grown GOI to various advanced functional devices.
•In-depth analysis of rapid-melting-grown Ge-on-insulator is performed.•The crystallinity of Ge-on-insulator is very high and uniform in-depth direction.•High hole mobility (~1000cm2/Vs) is achieved throughout the grown layers.
Low temperature (≤400°C) formation of orientation-controlled large (≥10µm) Ge-on-insulator (GOI) structures is desired to fabricate 3-dimensional large-scale integrated circuits (LSIs), where ...Ge-based functional devices are stacked on Si-LSIs. For this purpose, Si-seeded pulse-laser annealing (PLA) combined with low-temperature substrate heating (≤400°C) has been developed. Here, a-Ge stripes on Si substrates partially covered with insulating films are subjected to PLA, where single edges of the a-Ge stripes directly contact Si-seeding substrates through opening windows of insulating films. PLA at room temperature generates lateral growth of Ge layers from Si-seeding substrates. However, the growth length is short (~1µm), which is attributed to very short melting time. To increase the melting time, low-temperature (≤400°C) substrate heating during PLA is examined. As a result, very large (~20µm) orientation-controlled GOI is obtained by combining substrate heating (400°C) with PLA. Detailed electron microscopy analysis reveals very high crystallinity of the grown layers. Consequently, high-quality rapid-melting growth of Ge becomes possible at a low processing temperature of ~400°C. This thermally-assisted (~400°C) Si-seeded PLA will facilitate realization of 3-dimensional LSIs.
InSb thin film was deposited on glass by r.f. sputtering using the InSb (atomic ratio of 1:1) target. The film was capped by SiO2 film to prevent the effusion of Sb of low melting point. After that, ...blue laser beam at 445 nm of controlled power density was irradiated using CW scanning mode. The film was crystalized successfully with keeping the ratio of In and Sb as (1:1). High electron Hall mobility of 1,050 cm2/(Vs) was obtained without degrading under glass. New device applications such as magnetic or infrared sensor system with poly Si TFTs are expected not only on glass but also on flexible panel such as on plastic sheet.
Low-temperature formation (~150°C) of Ge films on insulator is investigated for realization of advanced flexible devices. We propose utilization of Sn as catalyst to enhance the crystallization at ...low-temperatures. By annealing (150–200°C) of a-Ge/Sn stacked structures formed on insulators, the composition distributions of Ge/Sn layers are inverted, and Sn/poly-Ge stacked structures are obtained. The results demonstrate that the crystallization occurs at 150°C, which is slightly below the eutectic temperatures. This Sn-induced crystallization technique is useful to obtain poly-Ge on low-cost flexible substrates (softening temperature: ~200°C).
•Low-temperature annealing (150–200°C) of a-Ge/Sn stacked structures is examined.•Polycrystalline–Ge is obtained after low-temperature annealing (~150°C).•This proves that layer-exchange growth occurs slightly below the eutectic temperatures.
Strain-induced enhancement of carrier mobility is essential for achieving high-speed transistors. The effects of thermal-annealing (temperature: 400–1150°C) and ultraviolet (UV) laser-annealing ...(wavelength: 248nm, temperature: 30–400°C) on strain-enhancement in Si-pillars covered with Si3N4 stress-liners by plasma-enhanced chemical vapor deposition are investigated. Before annealing, the Si3N4 stress-liners induce a tensile strain (~0.5%) in Si. After thermal-annealing (>800°C), the strain becomes highly compressive (> ~0.4%), because of dehydrogenation-induced structural relaxation in Si3N4 films. On the other hand, the tensile strain becomes large (>~0.7%) after UV laser-annealing at 400°C, due to non-equilibrium dehydrogenation in Si3N4 films. This strain-enhancement technique is useful for the realization of advanced high-speed three-dimensional transistors.
Our recent progress in low-temperature molecular beam epitaxy of ferromagnetic Heusler alloys on group-IV-semiconductor is reviewed. By optimizing beam flux ratio (Fe:Si
=
3:1) and growth temperature ...(130
°C), a high-quality hybrid structure, i.e., DO
3-type Fe
3Si on Ge with an atomically flat interface, was achieved. Excellent magnetic properties with a small coercivity (0.9
Oe) and electrical properties with Schottky barrier height of 0.52
eV were obtained. The ratio of the on-current to the off-current of Schottky diode was on the order of 10
4. In addition, heteroepitaxy of half-metallic alloys (Fe
3
−
X
Mn
x
Si(
X
=
0.6–1.4)) on Ge substrates was demonstrated. These results will be a powerful tool to open up group-IV-semiconductor spin-transistors, consisting of Ge channel with high mobility and ferromagnetic source/drain for spin-injection.
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