The emerging applications of silicon photonics in free space, such as LiDARs, free-space optical communications, and quantum photonics, urge versatile emission shaping beyond the capabilities of ...conventional grating couplers. In these applications, silicon photonic chips deliver free-space emission to detect or manipulate external objects. Light needs to emit from a silicon photonic chip to the free space with specific spatial modes, which produce focusing, collimation, orbital angular momentum, or even holographic projection. A platform that offers versatile shaping of free-space emission, while maintaining the CMOS compatibility and monolithic integration of silicon photonics is in pressing need. Here we demonstrate a platform that integrates metasurfaces monolithically on silicon photonic integrated circuits. The metasurfaces consist of amorphous silicon nanopillars evanescently coupled to silicon waveguides. We demonstrate experimentally diffraction-limited beam focusing with a Strehl ratio of 0.82. The focused spot can be switched between two positions by controlling the excitation direction. We also realize a meta-hologram experimentally that projects an image above the silicon photonic chip. This platform can add a highly versatile interface to the existing silicon photonic ecosystems for precise delivery of free-space emission.
Chip-scale photonic systems that manipulate free-space emission have recently attracted attention for applications such as free-space optical communications and solid-state LiDAR. Silicon photonics, ...as a leading platform for chip-scale integration, needs to offer more versatile control of free-space emission. Here we integrate metasurfaces on silicon photonic waveguides to generate free-space emission with controlled phase and amplitude profiles. We demonstrate experimentally structured beams, including a focused Gaussian beam and a Hermite-Gaussian TEM
beam, as well as holographic image projections. Our approach is monolithic and CMOS-compatible. The simultaneous phase and amplitude control enable more faithful generation of structured beams and speckle-reduced projection of holographic images.
A single-crystal islands (SCI) technique using low thermal budget pulse laser process is proposed and demonstrated to fabricate single-crystal silicon islands over amorphous dielectric for monolithic ...3-D and back-end-of-line (BEOL) FinFET circuits. By laser recrystallizing mask-defined a-Si islands encapsulated with conformal silicon nitride film, designed single-crystal Si islands can be obtained. The single crystallinity of the island are verified with SECCO Etch, high-resolution electron microscopy (HREM), transmission electron microscopy (TEM), and electron backside scattering (EBSD). About 40 nm FinFETs were successfully fabricated in the SCI Si islands and shown to exhibit excellent electrical performance and low variability that are compatible with the FinFETs fabricated on commercial silicon-on-insulator (SOI) wafer.
A back-end-of-line compatible 400 °C thermally robust perpendicular spin-orbit torque magnetic tunnel junction (p-SOT-MTJ) memory cell with a tunnel magnetoresistance ratio of 130% is demonstrated. ...It features an energy-efficient spin-transfer-torque-assisted field-free spin-orbit torque (SOT) switching and a novel interface-enhanced synthetic antiferromagnet (SAF). The optimal SAF with a Ru (9 Å) spacer sandwiched by Co/Pt multilayers has a high SAF coupling field of 2.8 kOe. The parallel magnetic coupling between the CoFeB-based reference layer and the bottom Co/Pt multilayer is enhanced by a magnet-coupling face-centered cubic textured Co/Pt (5 Å) multilayer buffer. The thermally induced Pt-Fe interdiffusion is effectively reduced by the W (3 Å) trilayers of texture-decoupling diffusion multibarrier. The Ta/<inline-formula> <tex-math notation="LaTeX">\beta </tex-math></inline-formula>-W and TaN/<inline-formula> <tex-math notation="LaTeX">\beta </tex-math></inline-formula>-W composite SOT channels are thick enough to be the etching stop and sustain 400 °C annealing without transforming to <inline-formula> <tex-math notation="LaTeX">\alpha </tex-math></inline-formula>-W. Using the harmonic Hall voltage measurement, the Ta/W and TaN/W channels exhibit the large effective spin Hall angle of approximately −0.21 and −0.27, respectively. Scaling magnetic tunnel junction (MTJ) down to 30 nm size can reduce the switching time due to single-domain switching based on the micromagnetic simulation. The damping constant of ~0.018 is obtained by the ferromagnetic resonance measurement. A bigger damping constant reduces the switching time as predicted by the calibrated simulation.
Back-end-of-line compatible 400°C thermally robust perpendicular spin-orbit torque (p-SOT) cells with reduced MgO short fails are demonstrated by the etch-stop-on-MgO process. The stop-on-MgO cell ...features the SOT channel continuity and no metal redeposition at MgO sidewall after ion beam etching. To the best of our knowledge, the endurance as high as 1010 cycles using the field-free spin-transfer torque (STT) assisted SOT writing is achieved for the first time. The SOT switching current density can be reduced by increasing the STT current density to save write energy. The stop-on-MgO cell does not degrade the cell switching speed, since the switching always starts from the inner free layer and the domain propagation at the extended free layer does not affect junction resistance, as shown by micromagnetic simulation. The simulation also reveals that the thermal stability factor of stop-on-MgO cells is enhanced by the extended free layer, which suffers less from the interference of pinned layer edge stray field.
A pulsed laser annealing method is utilized to directly synthesize nickel silicide (NiSi) as a contact material to improve the contact of electric devices. Three laser wavelengths, 355 nm ...(ultraviolet laser), 532 nm (green laser), and 1064 nm (infrared laser), are used for the NiSi synthesis during the pulsed laser annealing process. A NiSi phase with low sheet resistance is formed by an ultraviolet laser annealing (ULA) process without damaging the polyimide (PI) substrate. With the integration of the ULA process‐induced NiSi into p‐nnel MOSFET (PMOS) and n‐channel MOSFET (NMOS) devices, the on/off ratio improves significantly, and the field‐effect mobility increases by 30% because of the reduction in contact resistance from 21 to 8.5 kΩ. In addition to the PMOS and NMOS, the gains of the CMOS inverter at different Vdd values are improved by at least 30%. Moreover, the static noise margin of 6T‐SRAM is elevated from 0.82 to 1 V at Vdd = 4 V. The ability of the ULA process to synthesize a high‐quality NiSi layer on a flexible substrate is demonstrated. The integration of NiSi into electrical devices offers a new pathway for improving the electrical behavior of flexible devices.
A pulsed laser annealing method is applied to synthesize nickel silicide (NiSi) as a contact material. With the integration of NiSi into p‐channel MOSFET and n‐channel MOSFET devices, the on/off ratio improves and the field‐effect mobility increases because of a reduction in contact resistance.. In addition, the gains of the CMOS inverter are improved and the static noise margin of 6T‐SRAM is also increased.
Operation characteristics of polycrystalline germanium (poly-Ge) tri-gate junctionless (JL) charge-trapping (CT) flash memory devices with stacked tunneling layer were studied in this work. The ...programming speeds of poly-Ge tri-gate JL flash device with GeO x /Al 2 O 3 /SiO 2 tunneling layer are faster than those with GeO x /Al 2 O 3 or GeO x /SiO 2 ones, thanks to the modified electric field in the tunneling layer. Better retention characteristics are also achieved due to a larger barrier height and physical thickness, because Ge diffusion is effectively suppressed by adding an Al 2 O 3 between GeO x and SiO 2 , which can improve the quality of tunneling layer. A poly-Ge CT flash device fabricated with low-temperature process is promising for embedded memory in Ge CMOS or 3D IC.
Three-dimensional (3-D) nanostructures have demonstrated enticing potency to boost performance of photovoltaic devices primarily owning to the improved photon capturing capability. Nevertheless, ...cost-effective and scalable fabrication of regular 3-D nanostructures with decent robustness and flexibility still remains as a challenging task. Meanwhile, establishing rational design guidelines for 3-D nanostructured solar cells with the balanced electrical and optical performance are of paramount importance and in urgent need. Herein, regular arrays of 3-D nanospikes (NSPs) were fabricated on flexible aluminum foil with a roll-to-roll compatible process. The NSPs have precisely controlled geometry and periodicity which allow systematic investigation on geometry dependent optical and electrical performance of the devices with experiments and modeling. Intriguingly, it has been discovered that the efficiency of an amorphous-Si (a-Si) photovoltaic device fabricated on NSPs can be improved by 43%, as compared to its planar counterpart, in an optimal case. Furthermore, large scale flexible NSP solar cell devices have been fabricated and demonstrated. These results not only have shed light on the design rules of high performance nanostructured solar cells, but also demonstrated a highly practical process to fabricate efficient solar panels with 3-D nanostructures, thus may have immediate impact on thin film photovoltaic industry.
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