True-Time-Delay-Based Multi-Beam Arrays Ta-Shun Chu; Hashemi, Hossein
IEEE transactions on microwave theory and techniques,
08/2013, Volume:
61, Issue:
8
Journal Article
Peer reviewed
A broadband true-time-delay-based multi-beam array architecture is presented in this paper that is applicable to 1-D and 2-D linear antenna arrays. A 1-D millimeter-wave multi-beam array receiver and ...a 2-D ultra-wide band multi-beam array receiver have been implemented in 0.13- μm SiGe and a 0.13- μm CMOS technology, respectively. The 1-D millimeter-wave multi-beam array receiver with six antennas and seven beams covers the entire 30-40-GHz instantaneous bandwidth, and achieves 18° spatial resolution and ±54° spatial coverage with 4-mm antenna spacing. The 2-D ultra-wideband multi-beam array receiver with 2 × 2 antennas and 7 × 7 beams covers the 3-15-GHz instantaneous bandwidth, and achieves 10° spatial resolution and ±30° spatial coverage in each dimension with 3-cm antenna spacing.
This article describes a 10.7b 300MS/s two-step digital-slope analog-to-digital converter using an on-chip digital-offset correction. The proposed two-step digital-slope ADC is implemented using a ...passive track-and-hold followed by the input-polarity comparison and the two-step digital-slope conversion. The polarity of the input signal must be determined to control the level-shifting process and specify the operation polarity of the two-step digital-slope conversion. Besides, the two-step digital-slope conversion shares the unary DAC with different weights, which not only mitigates the resolution issues of the digital-slope quantizer but also converts the residue without requiring gain-error calibration. The two-step digital-slope ADC can be divided into three conversion steps and provide 1-bit, 5.7-bit, and 4-bit resolution for each conversion cycle. The digital-offset correction then encodes the three sets of outputs and subtracts the digital-offset caused by the feedback-process latency of the quantizers. The proposed two-step digital-slope ADC is manufactured using 1P9M 65-nm CMOS technology, and the active area of the prototype is 0.0946 square millimeter. At the Nyquist frequency, the SNDR and SFDR measured at 1.2 V, and 300 MS/s are 60.72 dB and 70.05 dB, respectively. With the power consumption of 6.2mW, the corresponding Walden FoM is 23.3 fJ/conversion-step.
This paper presents a direct-sampling pulsed radar with a high-resolution digital-to-time converter (DTC) for estimating the time of flight (TOF), which is to identify the distance between a target ...and radar. The implemented direct-sampling radar can reconstruct the scanning waveforms in digital domain. The link budget of the radar transceivers is analyzed for the overall scanning range. The scanning range of the radar is dependent on the TOF between radar transmitter and receiver. The range resolution of the pulsed TOF radar is determined by DTC. With the help of exquisite DTC, a high resolution radar can be achieved. The vernier concept has been adopted to achieve an accurate timing resolution design in the DTC. The vernier time steps are defined by the oscillating frequency of the phase-locked loops (PLL), and therefore the DTC with a high resolution in the order of picosecond and with high immunity to PVT variation was developed and demonstrated. The proposed radar was fabricated using 65 nm CMOS technology and occupies a chip area of 2 mm 2 , consumes 88.4 mW of DC power. The receiver has a 10 GHz instantaneous front-end bandwidth for capturing all scattering reflected waveforms and a 666 GS/s equivalent sampling rate for recording all received signals for subsequent digital signal processing (DSP) analysis.
This article presents a frequency interleaved technique (FIT) that can be applied to add resonant peaks in the response of distributed amplifier (DA) for loss compensation and then a ...frequency-interleaved distributed amplifier (FIDA) that can achieve a high-gain and wide-bandwidth frequency response by summing multiple overlapping distinct-band frequency responses through a distributed configuration. A detailed discussion was introduced to verify the FIDA and a DA was implemented using the FIT. The reported 65-nm CMOS FIDA chip occupies an area of <inline-formula> <tex-math notation="LaTeX">0.9\times 0.95\,\,\text {mm}^{2} </tex-math></inline-formula> and achieves a 17.2 dB small-signal power gain, 2-68 GHz −3-dB bandwidth, gain bandwidth product (GBW) of 478 GHz, and gain ripple of less than 2 dB, while consuming 120 mW under 1.2 V.
In this paper, a highly integrated frequency-modulated continuous-wave (FMCW) radar system with a single-antenna interface for range sensing is proposed. In this paper, a circulator structure was ...developed and used in the radar system with the single-antenna interface. This structure capitalizes on frequency orthogonality to separate transmitted and received signals; thus, the isolation can be improved by using integrated filters to further suppress transmitter leakage. Without an additional back-end leakage cancellation mechanism and antenna tuner, the single-antenna FMCW radar system can be devised. The proposed system is composed of a radar transceiver, a frequency synthesizer, an analog signal processor, and an AD converter; the system is fabricated using a 65-nm CMOS technology, occupies a chip area of 1.9 mm 2 , and consumes 147-mW dc power under a 1.2-V power supply. The implemented front-end circuit can provide an output power of 10.5 dBm with power efficiency of 30%, over 1-GHz impedance matching, an insertion loss of 2 dB, a maximum noise figure of 16.8 dB (including the following IF amplifier), <inline-formula> <tex-math notation="LaTeX">P_{1\,\text {dB}} </tex-math></inline-formula> of 2 dBm, and IIP 3 of 7 dBm. A wireless measurement process proved that the system can provide a 37-cm range resolution over a 50-m range for a <inline-formula> <tex-math notation="LaTeX">20 \times 20 </tex-math></inline-formula> cm 2 copper plate. Finally, an FMCW radar front-end board and a digital signal processing board were implemented for data analysis, thus completing the FMCW radar sensor unit. The proposed system can be utilized for multiple applications including 1-D object tracking, 2-D localization, and 3-D object tracking.
Phased array technology features rapid and directional scanning and has become a promising approach for remote sensing and wireless communication. In addition, element-level digitization has ...increased the feasibility of complicated signal processing and simultaneous multi-beamforming processes. However, the high cost and bulky characteristics of beam-steering systems have prevented their extensive application. In this paper, an X-band element-level digital phased array radar utilizing fully integrated complementary metal-oxide-semiconductor (CMOS) transceivers is proposed for achieving a low-cost and compact-size digital beamforming system. An 8–10 GHz transceiver system-on-chip (SoC) fabricated in 65 nm CMOS technology offers baseband filtering, frequency translation, and global clock synchronization through the proposed periodic pulse injection technique. A 16-element subarray module with an SoC integration, antenna-in-package, and tile array configuration achieves digital beamforming, back-end computing, and dc–dc conversion with a size of 317 × 149 × 74.6 mm3. A radar demonstrator with scalable subarray modules simultaneously realizes range sensing and azimuth recognition for pulsed radar configurations. Captured by the suggested software-defined pulsed radar, a complete range–azimuth figure with a 1 km maximum observation range can be displayed within 150 ms under the current implementation.
2-D Direct-Coupled Standing-Wave Oscillator Arrays Chen, Yen-Ju; Chu, Ta-Shun
IEEE transactions on microwave theory and techniques,
2013-Dec., 2013-12-00, 20131201, Volume:
61, Issue:
12
Journal Article
Peer reviewed
A direct-coupled technique for standing wave oscillator (SWO) arrays is presented in this paper. The oscillation currents of a unit cell in the SWO array directly inject to adjacent cells through the ...resonator. Two 2-D SWO arrays based on the technique are reported. The first SWO array can provide synchronous signals with identical frequencies, amplitudes, and phases at multiple locations over a chip. It is implemented in a 90-nm CMOS technology with 61.5-GHz oscillation frequency. Millimeter-wave radiators that consists of the proposed SWO array, an RF driver array, and an on-chip loop antenna array are implemented in a single chip to verify the synchronicity of the reported 2-D SWO via wireless measurement. The indirect evidence of synchronicity is provided from the correlation between the wireless measured effective isotropic radiated power (EIRP) and phase noise of 1 × 1, 2 × 2, and 3 × 3 arrays. The EIRP in the normal direction of the array is increasing by a factor of 10 log N 2 and the phase noise is reducing by a factor of 10 log N over that of a single cell, where N is the number of unit cells in the array. The second SWO array can provide synchronous signals with identical frequencies, amplitudes, and multiple phases at multiple locations over a chip. It is implemented in a 65-nm CMOS technology with 132.5-GHz fundamental frequency. The SWO array is designed for a 2-D second-harmonic (265 GHz) spatial power radiating and combining array. The EIRPs of the fundamental frequency and second harmonic in the normal direction of the array are -34 and -6.5 dBm, respectively. The phase noise of the fundamental frequency and second harmonic at 1-MHz offset from the carrier frequency are -96 and -89 dBc/Hz, respectively.
Complementary metal-oxide-semiconductor (CMOS) radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power ...wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP) is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA). The proposed reconstruction processor can support the 256 × 13 real-time radar image display with a throughput of 28.2 frames per second.
This paper presents a rotatable cyclic Vernier digital-to-time converter (DTC) with 1.8 ps timing resolution on an 80 ns time scale. The proposed DTC features high timing resolution, and can be ...utilized in beam-steering arrays, which is infeasible for ordinary Vernier DTCs. The proposed DTC was implemented within a passive time-equivalent direct-sampling ultra-wideband impulse-radio radar system and was fabricated in 65 nm CMOS technology. This radar system is capable of quantizing direct-sampled impulse waveforms to provide full degrees of freedom for backend digital signal processing. The measured differential nonlinearity/integral nonlinearity of the DTC was +4.6/−3 and 12.4/−9.4 where the LSB was 1.8 ps, and the total power consumption was 133 mW. Also, a new method for localization between wireless sensor nodes of equivalent-time direct-sampling radar is presented in this paper; this method can theoretically achieve resolution as high as that of regular radar.
This paper presents a radar system for extracting human respiratory features. The proposed radar chip comprises three major components: a digital-to-time converter (DTC), a transmitter, and a ...receiver. The all-digital standard cell-based DTC achieves a timing resolution of 10 ps on a 100-ns time scale, supporting a range-gated sensing process. The transmitter is composed of a digital pulse generator. The receiver comprises a direct-sampling passive frontend for achieving high linearity, an integrator for enhancing the signal-to-noise ratio, and a successive approximation register analog-to-digital converter for signal quantization. A fully integrated CMOS impulse radar chip was fabricated using 65-nm CMOS technology, and the total power consumption is 21 mW. In the backend, a real-time digital signal-processing platform captures human respiratory waveforms via the radar chip and processes the waveforms by applying a human respiratory feature extraction algorithm. Furthermore, a clinical trial was conducted for establishing a new diagnosis workflow for identifying respiratory diseases by the proposed wireless sensor system. The proposed system was validated by applying an adaptive network-based fuzzy inference system and support vector machine algorithm to the clinical trial results. These algorithms confirmed the effectiveness of the proposed system in diagnosing respiratory diseases.
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