A K-band ultra-wideband (UWB) pulse-compression (PC) automotive radar transmitter in 90-nm CMOS is presented, which is composed of the fully integrated pulse generator, mixer, driver amplifier, ...phase-locked loop, and timing circuitry. The PC technique with coding gain can effectively enhance the detection resolution and also improve the signal-to-noise ratio (SNR). We propose a PC transmitter allowing fast and precise code generation with small power consumption and chip area, and also offering reconfigurable capability. Compared with previously reported UWB pulse radars with relatively simple coding schemes, the proposed transmitter features a much more challenging 15-bit pseudonoise code design using high-speed shift registers, which can improve SNR up to 23.5 dB. The measured results demonstrate correct output waveforms corresponding to different modulation codes with the spectrum well confined under the regulation mask. With a modulation rate over 3 Gb/s (pulse repeat frequency of 6.125 MHz), a resolution of ~ 5 cm can be achieved.
This paper presents an ultra-wideband (UWB) impulse-radio radar signal processing platform used to analyze human respiratory features. Conventional radar systems used in human detection only analyze ...human respiration rates or the response of a target. However, additional respiratory signal information is available that has not been explored using radar detection. The authors previously proposed a modified raised cosine waveform (MRCW) respiration model and an iterative correlation search algorithm that could acquire additional respiratory features such as the inspiration and expiration speeds, respiration intensity, and respiration holding ratio. To realize real-time respiratory feature extraction by using the proposed UWB signal processing platform, this paper proposes a new four-segment linear waveform (FSLW) respiration model. This model offers a superior fit to the measured respiration signal compared with the MRCW model and decreases the computational complexity of feature extraction. In addition, an early-terminated iterative correlation search algorithm is presented, substantially decreasing the computational complexity and yielding negligible performance degradation. These extracted features can be considered the compressed signals used to decrease the amount of data storage required for use in long-term medical monitoring systems and can also be used in clinical diagnosis. The proposed respiratory feature extraction algorithm was designed and implemented using the proposed UWB radar signal processing platform including a radar front-end chip and an FPGA chip. The proposed radar system can detect human respiration rates at 0.1 to 1 Hz and facilitates the real-time analysis of the respiratory features of each respiration period.
In this letter, a wide tuning range W-band phase-locked loop (PLL) in 90 nm CMOS is presented. A novel frequency tripling topology with a single cross-coupled pair and a dual tank is proposed for the ...voltage-controlled oscillator (VCO) to achieve wide tuning characteristics under low power consumption. The locking range of the PLL at the fundamental tone is 25.4-29.7 GHz, and an excellent tuning range at the third harmonic frequency up to 12.9 GHz (from 76.2 to 89.1 GHz, 15.6%) is obtained. Under a 1.2 V supply voltage (P diss = 62.4 mW), the measured closed-loop phase noise of the PLL is -83.5 dBc/Hz at 78.34 GHz. To the best of our knowledge, the achieved turning range is the highest currently reported for the PLLs operating in a similar frequency range in CMOS technology.
A mixer-first single-RF-port duplexing RF frontend is proposed and implemented for frequency-modulated continuous-wave (FMCW) radar applications in this paper. The RF frontend is a bidirectional ...simultaneous frequency up-and-down converter. Equations of basic parameters of the frontend are derived to provide design criteria. The proposed radar architecture has been evaluated with an S-band (3.3-3.6 GHz) FMCW radar. The radar chip is fabricated in a 65nm CMOS process, and it consumes 190 mW of DC power under 1.2V supply. A wireless distance measurement has verified the function of the radar chip.
In this article, a scalable hybrid phased-array system is presented through synchronization, analog complex weighting, and digital beamforming of numerous fully integrated Ka-band four-receiver ...(RX)/four-transmitter (TX) phased-array transceiver integrated circuits (ICs). A 1.09-GHz clock synchronizes the local oscillator (LO) and a 50-MHz clock synchronizes analog-to-digital (A/D)/digital-to-analog (D/A) converters for all array elements. Phase shifting is first accomplished in the analog domain using optimal intermediate frequency (IF)/LO complex weighting and signal summing in the 4RX/4TX IC to reduce the number of signals by a factor of four, followed by A/D sampling and digital beamforming in field-programmable gate arrays (FPGAs) and central processing units (CPUs). Phase-shifting properties, programmable gain variations, and antenna patterns of each RTX channel are measured and tabulated to calculate the optimal channel weights. The long-term phase stability is enhanced through temperature control by monitoring all ICs' temperatures in real time and adaptively adjusting the duty cycle of the TX mode of each IC to limit instantaneous temperature variations to ±0.5 °C over each calibration session. This reduces random phase errors from 13.3° to 4.8° in the TX mode. After each Vivaldi antenna is located on a 2-D rectangular grid, an 8×4 subarray module with synchronized digital output is demonstrated. With the boresight pointing along the x̂-axis, the eight-element dimension pointing along the ŷ-axis, and the four-element dimension pointing along the ẑ-axis, this subarray steers radiation patterns with the E⃗ -field polarized to the ŷ-axis between ±40° in both azimuth and elevation with 13.4° and 26.4° measured 3-dB beamwidths, respectively.
The analysis, design, and implementation of an RF built-in self-test (BIST) bench on local oscillator phase noise are presented. An injection-locked-oscillator phase discriminator integrated with a ...2.56GHz phase-locked loop in 65nm CMOS is proposed in this bench. The proposed phase discriminator occupies an area of 0.38 mm×0.38 mm and consumes 3.8 mW of power. The RF-BIST bench provides the phase noise profile with 1.5dB, 1.4dB, and 2.7dB errors at 100kHz, 1MHz, and 10MHz offset frequencies respectively.
A 312GHz antenna array receiver is presented in this paper. The receiver is a double-conversion superheterodyne architecture. The first down-conversion is accomplished by a self-oscillating 3X ...subharmonic mixer frontend, and the second down-conversion is performed by a Gilbert-cell mixer and an LO. The receiver is co-designed and integrated with a 4-element loop antenna array. By mixing an RF input signal at 312 GHz with the 3 rd harmonic of the 96 GHz LO, the first IF of 24 GHz is produced (f IF1 =f RF -3f LO1 ). The second LO is at frequency of 22.3 GHz, and the second IF is 1.7 GHz (f IF2 =f IF1 -f LO2 ). The antenna array receiver exhibits a measured conversion loss of 19 dB from 312GHz RF to 1.7GHz IF, and has a -3dB bandwidth of 1.2 GHz. It is implemented in 65nm CMOS. The chip occupies an area of 1.71 mm 2 and consumes DC power of 110 mW.
For a pulsed Radar SoC, the programmable phase shifter is a critical timing control unit as it dictates the "time-of-arrival", i.e., the interval between the timing a pulse signal is launched and the ...timing an echo pulse is sampled. A pulsed Radar SoC often sweeps this timing parameter (from a smaller value to a larger value) to set the distance of detection of an object in a scanning fashion from the center of the Radar towards the outer regions. In this paper, we demonstrate that such a programmable phase shifter can be designed with only standard cells, while being able to control the time-of-arrival in 10,000 steps with a step size of 10ps within a wide tunable range of 0ns, 10ns. Measurements results in a 65nm process are reported.
Intelligent environments significantly impact human daily lives through embedded sensing and actuating systems. Wireless sensors that can provide non-contact radio information are indispensable. ...Impulse radar is positioned as a favorable candidate in monitoring and sensing objects 1-3. The impulse radio is inherently multipath immune and suitable for precision ranging. Accurately detecting signals with low power impulse radios imposes design challenges to impulse radar receivers. In this work, a direct-sampling receiver is proposed and implemented for an impulse radar system. It can support GHz instantaneous bandwidth and more than 100GS/sec equivalent sampling rate through the high-speed sampling circuits and on-chip timing circuitry. The wide bandwidth scattering time-domain waveforms in the radio interaction between the object and radar can be sampled and digitized by the receiver. It achieves precise measurement of time of arrival (TOA) in a radar system and expands the scalability towards antenna arrays for detection of direction of arrival (DOA) 4.
This paper presents a ultra-wideband (UWB) impulse radio timed-array radar utilizing time-shifted direct-sampling architecture. Time shift between the sampling time of the transmitter and the ...receiver determines the time of arrival (TOA), and a four-element timed antenna array enables beamforming. The different time shifts among the channels at the receiver determine the object's direction of arrival (DOA). Transmitter channels have different shifts, as well, to enhance spatial selectivity. The direct-sampling receiver reconstructs the scattered waveform in the digital domain, which provides full freedom to the backend digital signal processing. The on-chip digital-to-time converter (DTC) provides all the necessary timing with a fine resolution and wide range. The proposed architecture has a range and azimuth resolution of 0.75 cm and 3 degrees, respectively. The transmitter is capable of synthesizing a variety of pulses within 800 ps at a sampling rate of 10 GS/s. The receiver has an equivalent sampling frequency of 20 GS/s while supporting the RF bandwidth from 2 to 4 GHz. The proposed designs were fabricated in a 0.18- μm standard CMOS technology with a die size of 5.4×3.3 mm 2 and 5.4×5.8 mm 2 for the transmitter and the receiver, respectively.
