A 79GHz UWB pulse-compression (PC) vehicular radar system is presented. A PC waveform is a long pulse with internal modulation. The energy of it can be increased without raising the instantaneous ...peak power. Meanwhile, a PC waveform preserves an equal bandwidth and the range resolution associated with a single pulse waveform. In addition, the PC technique also allows multiple radars operating simultaneously based on the code division multiple accessing (CDMA). In this work, the internal modulation of the PC waveform is binary phase shift keying (BPSK) with a 31-bit length pseudo noise (PN) sequence. The modulation rate is 1 Gb/s and the maximum pulse width is 31 nsec. The CMOS chip presents a self-contained radar system with the transmitter, receiver, frequency synthesizer, and complete timing circuit fully integrated in a standard 90nm CMOS technology.
A fully integrated CMOS ultra-wideband 4-channel timed array receiver for high-resolution imaging application is presented. A path-sharing true time delay architecture is implemented to reduce the ...chip area for integrated circuits. The true time delay resolution is 15 ps and the maximum delay is 225 ps. The receiver provides 11 scan angles with almost 9 degrees of spatial resolution for an antenna spacing of 3 cm. The design bandwidth is from 1 to 15 GHz corresponding to less than 1 cm depth resolution in free space. The chip is implemented in 0.13 mum CMOS with eight metal layers, and the chip size is 3.1 mm by 3.2 mm. Measurement results for the standalone CMOS chip as well as the integrated planar antenna array and the CMOS chip are reported.
In this paper, a UWB imaging camera with 7x7 active pixels is reported. The UWB camera consists of a CMOS chip that interfaces with 2x2 3D omni-directional UWB antennas. This receiving camera forms ...7x7 simultaneous beams in two dimensions and includes an array of on-chip pulse-energy detectors for each active pixel. With 3cm of spacing between antenna elements, this 2D UWB camera achieves a 10deg spatial resolution and plusmn30deg of spatial coverage in each dimension.
Frequency-modulated continuous-wave (FMCW) radars can provide high resolution and superior sensitivity for wireless sensing 1-3. Radar signals, whose frequency increases or decreases linearly with ...time, are transmitted via an antenna, reflected from an object, and then received through an antenna after a time delay. Therefore, the frequency difference between the transmitted and received signals can define the distance and speed of objects. There are two approaches of interfacing antenna for a FMCW radar, namely two-antenna (i.e. separated-antenna) and single-antenna (i.e. shared-antenna) methods. A single-antenna FMCW radar is more compact, but more difficult to implement than a two-antenna one. On-chip in-band full duplexers (IBFDs) with a self-interference cancellation mechanism can support general integrated single-antenna wireless systems 4-6. For the specific application of a FMCW radar, a duplex RF front-end without the complexity of on-chip IBFDs has been proposed. With it, an integrated FMCW radar is allowed to transmit and receive simultaneously via a single antenna. In this work, an integrated X-band FMCW radar chip is implemented in 65nm CMOS and a wireless demonstration of the radar chip is presented.
This paper presents a ultra-wideband (UWB) impulse radio timed-array radar utilizing time-shifted direct-sampling architecture. Time shift between the sampling time of the transmitter and the ...receiver determines the time of arrival (TOA), and a four-element timed antenna array enables beamforming. The different time shifts among the channels at the receiver determine the object's direction of arrival (DOA). Transmitter channels have different shifts, as well, to enhance spatial selectivity. The direct-sampling receiver reconstructs the scattered waveform in the digital domain, which provides full freedom to the backend digital signal processing. The on-chip digital-to-time converter (DTC) provides all the necessary timing with a fine resolution and wide range. The proposed architecture has a range and azimuth resolution of 0.75 cm and 3 degrees, respectively. The transmitter is capable of synthesizing a variety of pulses within 800 ps at a sampling rate of 10 GS/s. The receiver has an equivalent sampling frequency of 20 GS/s while supporting the RF bandwidth from 2 to 4 GHz. The proposed designs were fabricated in a 0.18- mu rmm standard CMOS technology with a die size of syntax error at token } and syntax error at token } for the transmitter and the receiver, respectively.
This paper presents a ultra-wideband (UWB) impulse radio timed-array radar utilizing time-shifted direct-sampling architecture. Time shift between the sampling time of the transmitter and the ...receiver determines the time of arrival (TOA), and a four-element timed antenna array enables beamforming. The different time shifts among the channels at the receiver determine the object's direction of arrival (DOA). Transmitter channels have different shifts, as well, to enhance spatial selectivity. The direct-sampling receiver reconstructs the scattered waveform in the digital domain, which provides full freedom to the backend digital signal processing. The on-chip digital-to-time converter (DTC) provides all the necessary timing with a fine resolution and wide range. The proposed architecture has a range and azimuth resolution of 0.75 cm and 3 degrees, respectively. The transmitter is capable of synthesizing a variety of pulses within 800 ps at a sampling rate of 10 GS/s. The receiver has an equivalent sampling frequency of 20 GS/s while supporting the RF bandwidth from 2 to 4 GHz. The proposed designs were fabricated in a 0.18-Formula Omitted standard CMOS technology with a die size of Formula Omitted and Formula Omitted for the transmitter and the receiver, respectively.
This paper describes the design and implementation of an X-band scalable 4\times 4 element-level digital phased array module. The module consists of sixteen active antenna elements. Each of these ...elements includes one custom CMOS RF SoC and one custom GaAs switch frontend IC. The RF SoC is implemented using a 65-nm CMOS process. The T/R Switch frontend IC is implemented in a 0.15-\mu \mathrm{m} GaAs pHEMT process. The module also includes a digital signal processor implemented in an FPGA SoC device, and the required power supply subsystems. This module can be used to build a large hierarchical digital phased array through synchronizing four LO signals at system level. The built array serves as a tool for researching software-defined phased array radar and communication systems. This paper reports initial test results of this module. This module achieves a state-of-the-art 42-mm scalable tile thickness.
碩士
國立臺灣大學
應用力學研究所
90
Miniaturization of optical devices is increasingly needed in optical communication, imaging, and instrumentation. In the recent years, micro optics using MEMS techniques has been ...gradually playing an important role. The thesis first presents a novel addressable corner micromirror array for wide free-space optical applications. The corner mirror, composed of two mutually orthogonal reflective surfaces, may reflect incident light beam at any angle back of one specific plane to its incoming direction. Each micromachined corner mirror is constituted by three elements: a vertical mirror, a movable horizontal mirror, and a bottom electrode.
In microfabrication, the bulk micromachining is used to fabricate all three opto-mechanical elements that bulk material of single crystal silicon provides superior opto-mechanical properties of polished surface, flatness and low residual stress. Meanwhile, the vertical mirrors are anisotropically bulk-micromachined with a (110) Si wafer for virtually vertica
This paper presents a fully-integrated Ka-band 4RX/4TX phased-array transceiver IC. The four transceiver channels are synchronized by an I/Q standing wave oscillator (SWO). Their signal phases are ...shifted by hybrid analog IF and LO phase interpolators, and can be controlled digitally and independently. The SWO further composes an on-chip PLL, and is locked to a 1.09 GHz off-chip global reference to scale to a large array at board level. Each receiver channel achieves 66 dB maximum conversion gain and 4.4 dB minimum noise figure. Each transmitter channel achieves 18 dBm maximum output power. The chip is mounted on a high-frequency laminate, inside which embedded cables connect its RF pads to Vivaldi antennas also inside the same PCB. With the PCB, each channel achieves 360° phase shifting capability under a maximum calibrated 3.7° phase errors. The PCB module presents successful beam steering with 23° measured four-channel 3-dB beamwidth. This chip consumes a peak 5 W power at transmit mode, and is fabricated in TSMC 65nm CMOS technology with a 4 × 2.5 mm2 chip area.
