Deep n-well MAPS in a 130 nm CMOS technology: Beam test results Lusiani, A; Manghisoni, M; Re, V ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
11/2010, Volume:
623, Issue:
1
Journal Article
Peer reviewed
We report on recent beam test results for the APSEL4D chip, a new deep n-well MAPS prototype with a full in-pixel signal processing chain obtained by exploiting the triple well option of the CMOS ...inline image process. The APSEL4D chip consists of a 4096 pixel matrix (32 rows and 128 columns) with inline image pixel cell area, with custom readout architecture capable of performing data sparsification at pixel level. APSEL4D has been characterized in terms of charge collection efficiency and intrinsic spatial resolution under different conditions of discriminator threshold settings using a 12 GeV/c proton beam in the T9 area of the CERN PS. We observe a maximum hit efficiency of 92% and we estimate an intrinsic resolution of about inline image. The data driven approach of the tracking detector readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on associative memories. The analysis of the beam test data is critically reviewed along with the characterization of the device under test.
The paper describes a mixed-mode ASIC composed of a fast readout architecture that interfaces with a matrix of 4096 Monolithic Active Pixel Sensors (MAPS). The matrix has 128 columns and 32 rows of ...pixels and is divided into 256 regions of 4 times 4 pixels, named macro-pixels (MPs). The chip is an upgrade of a smaller version having 256 pixels that was designed and tested. The two chips were designed via STM 130 nm CMOS technology. The pixel dimension is 50 by 50 mum 2 . The work is aimed at improving the design of MAPS detectors with an on-chip fast sparsification system, for particle tracking, to match the requirements of future high-energy physics experiments. The readout architecture implemented is data driven to extend the flexibility of the system, to be also used in first level triggers on tracks in vertex detectors. Simulations indicate that the readout system can cope with an average hit rate up to 100 MHz/cm 2 if a master clock of 80 MHz is used, while maintaining an overall efficiency over 99%.
Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and luminosity increase we need increasingly ...exclusive selections to efficiently select the rare events inside the huge background. We present a fast, high-quality, track-based event selection for the self-triggered SLIM5 silicon telescope. This is an R&D experiment whose innovative trigger will show that high rejection factors and manageable trigger rates can be achieved using fine-granularity, low-material tracking detectors.
The data acquisition system of the SuperB-SVT beam test Sbarra, C.; Fabbri, L.; Gabrielli, A. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
08/2013, Volume:
718
Journal Article
Peer reviewed
Prototypes of a new hybrid pixel detector and a high resistivity detector with short strips, developed by the VIPIX Collaboration and aimed at equipping the layer-0 of the SuperB vertex detector, ...have been tested in September 2011 with a 120GeV pion beam at the SPS H6 beam line at CERN. They are placed at the center of a reference telescope consisting of six planes of silicon detector with a double-sided strip readout. Both the telescope and the detectors under test (DUT) are equipped with a custom-design, data-push digital readout. The main elements of the trigger and data acquisition system are two VME boards (EDRO) organized in a master-slave configuration and responsible for programming the front-end chips of both the telescope and the DUT. The master board distributes a global synchronization clock and the triggers to all devices, including two 3×3 analog-maps matrices placed behind the DUT and supplied with an independent readout. Both EDROs act as event-fragment builders. These are sent out to a remote PC for event building, buffering and storage.
The SLIM5 low mass silicon tracker demonstrator Bettarini, S.; Ratti, L.; Rizzo, G. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
11/2010, Volume:
623, Issue:
3
Journal Article
Peer reviewed
A low material budget silicon demonstrator has been tested by the SLIM5 collaboration with 12
GeV/
c protons at the PS-T9 beam line at CERN. Two devices were placed inside a reference telescope and ...their characteristics were measured. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130
nm CMOS technology, providing digital sparsified readout. The other one was a high resistivity double-sided silicon detector, with short strips at a
45
∘
angle to the detector's edge, read out by the FSSR2 chip. In this paper we describe the main features of both sensors. The primary goal of the test was to measure the efficiency and the resolution of the DUTs under different conditions of threshold setting and incident angle of the impinging particles. The data-driven approach of the readout chips has been fully exploited by the DAQ system to take data with a track-based level-1 trigger provided by a pattern matching algorithm with very low latency.
In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius ...(about 1.5cm), resolution of 10–15μm in both coordinates, low material budget <1%X0, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180nm process and the 130nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.
The front-end chip of the SuperB SVT detector Giorgi, F.; Comotti, D.; Manghisoni, M. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
08/2013, Volume:
718
Journal Article
Peer reviewed
Open access
The asymmetric e+e− collider SuperB is designed to deliver a high luminosity, greater than 1036cm−2s−1, with moderate beam currents and a reduced center of mass boost with respect to earlier ...B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2MHz per strip, the efficiency of the digital readout remained above 99.8%.
Beam test results for the SuperB-SVT thin striplet detector Fabbri, L.; Comotti, D.; Manghisoni, M. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
08/2013, Volume:
718
Journal Article
Peer reviewed
Open access
The baseline detector option for the first layer of the SuperB Silicon Vertex Tracker (SVT) is a high resistivity double-sided silicon device with short strips (striplets) at 45° angle to the ...detector's edge. A prototype was tested with a 120GeV/c pion beam in September 2011 at the SPS-H6 test-beam line at CERN. In this paper studies on efficiency, resolution and cluster size are reported.
PDF
