Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary ...metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.
Silicon spin qubits have emerged as a promising path to large-scale quantum processors. In this prospect, the development of scalable qubit readout schemes involving a minimal device overhead is a ...compelling step. Here we report the implementation of gate-coupled rf reflectometry for the dispersive readout of a fully functional spin qubit device. We use a p-type double-gate transistor made using industry-standard silicon technology. The first gate confines a hole quantum dot encoding the spin qubit, the second one a helper dot enabling readout. The qubit state is measured through the phase response of a lumped-element resonator to spin-selective interdot tunneling. The demonstrated qubit readout scheme requires no coupling to a Fermi reservoir, thereby offering a compact and potentially scalable solution whose operation may be extended above 1 K.
Spins in silicon quantum devices are promising candidates for large-scale quantum computing. Gate-based sensing of spin qubits offers a compact and scalable readout with high fidelity, however, ...further improvements in sensitivity are required to meet the fidelity thresholds and measurement timescales needed for the implementation of fast feedback in error correction protocols. Here, we combine radio-frequency gate-based sensing at 622 MHz with a Josephson parametric amplifier, that operates in the 500-800 MHz band, to reduce the integration time required to read the state of a silicon double quantum dot formed in a nanowire transistor. Based on our achieved signal-to-noise ratio, we estimate that singlet-triplet single-shot readout with an average fidelity of 99.7% could be performed in 1 μs, well below the requirements for fault-tolerant readout and 30 times faster than without the Josephson parametric amplifier. Additionally, the Josephson parametric amplifier allows operation at a lower radio-frequency power while maintaining identical signal-to-noise ratio. We determine a noise temperature of 200 mK with a contribution from the Josephson parametric amplifier (25%), cryogenic amplifier (25%) and the resonator (50%), showing routes to further increase the readout speed.
We report the dispersive readout of the spin state of a double quantum dot formed at the corner states of a silicon nanowire field-effect transistor. Two face-to-face top-gate electrodes allow us to ...independently tune the charge occupation of the quantum dot system down to the few-electron limit. We measure the charge stability of the double quantum dot in DC transport as well as dispersively via in situ gate-based radio frequency reflectometry, where one top-gate electrode is connected to a resonator. The latter removes the need for external charge sensors in quantum computing architectures and provides a compact way to readout the dispersive shift caused by changes in the quantum capacitance during inter-dot charge transitions. Here, we observe Pauli spin-blockade in the high-frequency response of the circuit at finite magnetic fields between singlet and triplet states. The blockade is lifted at higher magnetic fields when intra-dot triplet states become the ground state configuration. A line shape analysis of the dispersive phase shift reveals furthermore an intra-dot valley-orbit splitting Δ vo of 145 μeV. Our results open up the possibility to operate compact complementary metal-oxide semiconductor (CMOS) technology as a singlet–triplet qubit and make split-gate silicon nanowire architectures an ideal candidate for the study of spin dynamics.
Hole spins in silicon represent a promising yet barely explored direction for solid-state quantum computation, possibly combining long spin coherence, resulting from a reduced hyperfine interaction, ...and fast electrically driven qubit manipulation. Here we show that a silicon-nanowire field-effect transistor based on state-of-the-art silicon-on-insulator technology can be operated as a few-hole quantum dot. A detailed magnetotransport study of the first accessible hole reveals a g-factor with unexpectedly strong anisotropy and gate dependence. We infer that these two characteristics could enable an electrically driven g-tensor-modulation spin resonance with Rabi frequencies exceeding several hundred mega-Hertz.
One consequence of the continued downward scaling of transistors is the reliance on only a few discrete atoms to dope the channel, and random fluctuations in the number of these dopants are already a ...major issue in the microelectronics industry. Although single dopant signatures have been observed at low temperatures, the impact on transistor performance of a single dopant atom at room temperature is not well understood. Here, we show that a single arsenic dopant atom dramatically affects the off-state room-temperature behaviour of a short-channel field-effect transistor fabricated with standard microelectronics processes. The ionization energy of the dopant is measured to be much larger than it is in bulk, due to its proximity to the buried oxide, and this explains the large current below threshold and large variability in ultra-scaled transistors. The results also suggest a path to incorporating quantum functionalities into silicon CMOS devices through manipulation of single donor orbitals.
In the standard MOSFET description of the drain current <inline-formula> <tex-math notation="LaTeX"> {I}_{{D}} </tex-math></inline-formula> as a function of applied gate voltage <inline-formula> ...<tex-math notation="LaTeX"> {V}_{{ {GS}}} </tex-math></inline-formula>, the subthreshold swing <inline-formula> <tex-math notation="LaTeX">{{SS(T)}}\equiv {{dV}}_{{{GS}}}/ {d}\log {I}_{ {D}} </tex-math></inline-formula> has a fundamental lower limit as a function of temperature <inline-formula> <tex-math notation="LaTeX">{T} </tex-math></inline-formula> given by <inline-formula> <tex-math notation="LaTeX">{ {SS(T)}}=\ln 10\,\, {k}_{ {B}} {T}/ {e} </tex-math></inline-formula>. However, recent low-temperature studies of different advanced CMOS technologies have reported SS (4 K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of SS(T) in 28 nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4 K. Until now, the increase of interface-trap density close to the band edge as temperature decreases has been put forward to understand the saturation. Here, an original explanation of the phenomenon is presented by considering a disorder-induced tail in the density of states at the conduction (valence) band edge for the calculation of the MOS channel transport by applying the Fermi-Dirac statistics. This results in a subthreshold <inline-formula> <tex-math notation="LaTeX"> {I}_{ {D}}\sim {e}^{{{ {eV}}}_{{{GS}}}/ {k}_{ {B}} {T}_{0}} </tex-math></inline-formula> for <inline-formula> <tex-math notation="LaTeX"> {T}_{0}=35 </tex-math></inline-formula> K with saturation value <inline-formula> <tex-math notation="LaTeX">{ {SS}}( {T}< {T}_{0})= \ln 10\,\, {k}_{ {B}} {T}_{0}/ {e} </tex-math></inline-formula>. The proposed model adequately describes the experimental data of SS(T) from 300 down to 4 K using <inline-formula> <tex-math notation="LaTeX"> {k}_{ {B}} {T}_{0} \simeq 3 </tex-math></inline-formula> meV for the width of the exponential tail and can also accurately describe <inline-formula> <tex-math notation="LaTeX">{ {SS}}( {I}_{ {D}}) </tex-math></inline-formula> within the whole subthreshold region. Our analysis allows a direct determination of the technology-dependent band-tail extension forming a crucial element in future compact modeling and the design of cryogenic circuits.
Self-heating in fully depleted silicon-on-insulator (FDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in ...a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase (<inline-formula> <tex-math notation="LaTeX">\Delta {T} </tex-math></inline-formula>) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature (<inline-formula> <tex-math notation="LaTeX">{T}_{\text {Device}} </tex-math></inline-formula>) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work.
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