In this letter, the electrostatic and the performance of cylindrical silicon nanowire (NW) MOSFETs with an omega-shaped gate and diameters down to 8 nm are investigated. The impact of silicon nitride ...(SiN) spacer thickness (7, 10, or 15 nm) on short-channel performance is examined. The tradeoff between superior electrostatic confinement and electrical performance, which will be an essential consideration for the design of future NW devices, is clearly observed. Finally, a comparison with trigate NWs shows an improved electrostatic control for a cylindrical-shaped gate, as theoretically expected.
In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back ...end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 °C during a couple of hours. Then, the full LT process flow with process modules developed at 500 °C is exposed. Great progress and breakthrough for high performance (HP) digital stacked FETs has been made recently. Areas previously considered as potential showstoppers have been overcome: 1) efficient contamination containment for wafers with Cu/ultra low-<inline-formula> <tex-math notation="LaTeX">{k} </tex-math></inline-formula> (ULK) iBEOL enabling their reintroduction in front end of line (FEOL) for top FET processing; 2) low-resistance poly-Si gate for the top FETs and solutions for improving gate-stack reliability; and 3) full LT raised source drain (RSD) epitaxy including surface preparation combined with SiCO 400 °C spacer and SPER junctions activation. Finally, the first functional nMOS and pMOS demonstration with a 500 °C thermal budget (TB) is highlighted.
A three dimensional 300 mm wafer scale nano imprinting lithography was developed. Two process flows were investigated to manufacture sub 100 nm resolution multilevel silicon stamps. Using 193 nm ...optical lithography and dry etching processes in a standard Integrated Circuit pilot line, we succeeded in manufacturing 5 levels stamps. Depending of the pattern designs and number of required levels onto the stamp, we proposed manufacturing process rules. We also demonstrated that sub 20 nm overlay accuracy over 300 mm wafer was achievable between each level patterned into the stamp. These 3D stamps were then printed over 300 mm wafer coated with 200 nm thick thermoplastic resist layer. We demonstrated that large surface 3D printing with sub 100 nm resolution was achievable with an equivalent patterning throughput of 4 cm super(2)/s. Both the use of silicon hard and polymer soft 3D stamps were investigated to underline the impact of the stamp's mechanical stiffness onto the residual layer thickness distribution over large surfaces.
•300mm wafer scale stamp manufacturing.•300mm thermal nano imprint lithography.•3D sub 100nm wafer scale imprinting with sub 20nm overlay accuracy.
A three dimensional 300mm wafer scale nano ...imprinting lithography was developed. Two process flows were investigated to manufacture sub 100nm resolution multilevel silicon stamps. Using 193nm optical lithography and dry etching processes in a standard Integrated Circuit pilot line, we succeeded in manufacturing 5 levels stamps. Depending of the pattern designs and number of required levels onto the stamp, we proposed manufacturing process rules. We also demonstrated that sub 20nm overlay accuracy over 300mm wafer was achievable between each level patterned into the stamp. These 3D stamps were then printed over 300mm wafer coated with 200nm thick thermoplastic resist layer. We demonstrated that large surface 3D printing with sub 100nm resolution was achievable with an equivalent patterning throughput of 4cm2/s. Both the use of silicon hard and polymer soft 3D stamps were investigated to underline the impact of the stamp’s mechanical stiffness onto the residual layer thickness distribution over large surfaces.
For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) ...process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.
In this paper we show that on scaling nanowire width from 20 nm down to sub-7 nm regime, together with achieving excellent short channel effect control (DIBL = 12 mV/V for LG = 20 nm), we hit a ...dramatic transition in transport mechanism from monotonously increasing IDaVG of a FET to oscillating IDaVG of a Single Electron Transistor. This transition in transport mechanism is brought about by process induced channel potential variability. It poses a challenge to further scaling of nanowire MOSFETs. However, we show that it provides an exciting opportunity to cointegrate Single Electron Transistors with high-k/metal gate operating at room temperature (at VD = A-0.9 V) with the state-of-the-art nanowire MOSFETs enabling large scale manufacturing of Beyond Moore devices.
We report an experimental study of the carrier transport in 110-oriented long channel tri-gate (TG) and omega-gate (ΩG) silicon nanowire (SiNW) transistors cross-section down to 11nm×10nm. Electron ...and hole mobilities have been measured down to 20K to evaluate the contribution from the dominant scattering mechanisms. We have studied and discussed the influence of channel shape, channel width and strain effect on carrier mobility. In particular, we have shown that the transport properties are mainly driven by the relative contribution of the different inversion surfaces, without noticeable differences between TG and ΩGNWs. We have also demonstrated the effectiveness of an additional uniaxial tensile strain in NMOS NWs down to 10nm width.
Thanks to bonding, metal-gate etching without any out-of-gate Si consumption, and self-aligned transfer of alignment marks, we have processed the first 10-nm-gate-length DG MOS transistors with metal ...gates. These devices exhibit excellent short-channel effects control and high-performance characteristics. Their saturation current is very sensitive to the access resistance increase caused by film thinning required to respect the scaling rules. Moreover, their electrical properties can be tuned between LSTP and HP by independently biasing the two gates.
For the first time FDSOI CMOS transistors with Si- monocrystalline channel have been fabricated at a temperature below 500°C. High performance PMOS (Ion=450μA/μm (V dd -0.9V) @ Ioff=-2nA/μmLg=35nm) ...with low overlap capacitance (0.46fF/μm per device), low gate resistance (10Ω) at Low Temperature (L T) enables to achieve good RF Figure-Of-Merit (FOM) with Fmax values up to 170GHz. In addition, we demonstrate for the first time the full functionality of Ring Oscillators (RO) and SRAM bitcells processed at 500°C, paving the way for a high-performance 3D sequential CMOS integration.
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