We present an experimental study to compare the impacts of different dielectric materials - Al 2 O 3 and SiO 2 used as the tunnel dielectric layer (TDL) and the gate blocking layer (GBL) on the ...performance of ferroelectric gate stacks for NAND storage applications. We considered the maximum memory window (MW) and the incremental step program pulse (ISPP) slope as the key performance metrics. In a gate stack with TDL, Al 2 O 3 gives higher MW and ISPP performance than SiO 2 . However, in the GBL gate stack, SiO 2 has a higher MW and ISPP slope than Al 2 O 3 . With SiO 2 GBL, a maximum MW window of 8.3V was achieved, enabling quad-level cell (QLC) capability. We show that for a similar thickness, SiO 2 as GBL has the better MW performance, and Al 2 O 3 as TDL has a better ISPP performance. This study shows that TDL and GBL with appropriate dielectric material can be used as tuning knobs to achieve the desired ISPP and MW performance for ferroelectric NAND applications.
Basic gate stack structure of the Ferroelectric FET is Metal-ferroelectric-insulator-silicon (MFIS), where the memory window (M.W) is <inline-formula> <tex-math notation="LaTeX">2^{\ast } ...</tex-math></inline-formula>(Pr-Q<inline-formula> <tex-math notation="LaTeX">_{\text {it}}\text {)} </tex-math></inline-formula>/CFE considering the trapped charge. However, in Metal - insulator - ferroelectric - insulator - silicon (MIFIS) gate-stacked FeFETs, the M.W is <inline-formula> <tex-math notation="LaTeX">2^{\ast } </tex-math></inline-formula>{(Pr-Q<inline-formula> <tex-math notation="LaTeX">_{\text {it}}\text {)} </tex-math></inline-formula>/C<inline-formula> <tex-math notation="LaTeX">_{\text {FE}} + </tex-math></inline-formula> (Q'it-Q<inline-formula> <tex-math notation="LaTeX">_{\text {it}}\text {)} </tex-math></inline-formula>/C<inline-formula> <tex-math notation="LaTeX">_{\text {G. {IL}}}\text {)} </tex-math></inline-formula>}, which allows the M.W to widen in case the Q'it injected from the gate side is larger than the Qit injected from the channel side. In this letter, we propose a band engineered (BE) gate insulator in MIFIS gate-stacked FeFETs. This lowers the energy barrier of the hole when applying the program voltage, thereby increasing the amount of hole injected from the gate side, and consequently widening the M.W. Furthermore, it is demonstrated by TCAD simulation that the physical origins of Vt shift of PGM state is hole injection. In addition, in the case of BE-MIFIS gate-stacked FeFETs, the maximum ISPP slope is increased by about 2 times compared to conventional MIFIS, which is an important feature in ferroelectric VNAND (FeVNAND) operated at low voltage.
In this letter, we present highly linear potentiation/depression behaviors of a neuromorphic synaptic device made of CMOS-compatible floating gate (FG) cells. The kinetics of the charge trap/detrap ...mechanism under various pulse shapes are analyzed to design a simple 2C-4T FG cell with a modulated column write driver for embedded incremental step pulse programming (ISPP) via analog feedback. Utilizing real-time ISPP, the linearity and symmetry of the weight update were significantly improved due to the content-aware programming strength. Moreover, the proposed circuit technique provides flexibility regarding the size of the program/erase steps in addition to the superior linearity. The proposed FG cells with peripheral circuits are fabricated using 180nm CMOS technology and exhibited a differential non-linearity (DNL) less than 0.946 least significant bit (LSB) with 100 weight states. The excellent linearity remains unchanged even when the directions of potentiation /depression are reversed throughout the entire range.
In order to improve the reliability of vertical NAND (V-NAND) flash memory cells, a scheme using adaptive incremental step pulse programming (A-ISPP) and incremental step pulse erasing (ISPE) is ...proposed. Incremental step pulse programming (ISPP) with adaptive step voltage is used to precisely adjust <inline-formula> <tex-math notation="LaTeX">{V}_{\text {th}} </tex-math></inline-formula> to a low target value while rapidly increasing <inline-formula> <tex-math notation="LaTeX">{V}_{\text {th}} </tex-math></inline-formula> to a high target value. By applying ISPE after A-ISPP, an accurate <inline-formula> <tex-math notation="LaTeX">{V}_{\text {th}} </tex-math></inline-formula> with improved retention characteristics is obtained at a high target <inline-formula> <tex-math notation="LaTeX">{V}_{\text {th}} </tex-math></inline-formula> level. Compared to the conventional ISPP, the proposed scheme improves adjusted <inline-formula> <tex-math notation="LaTeX">{V}_{\text {th}} </tex-math></inline-formula> accuracy and <inline-formula> <tex-math notation="LaTeX">{V}_{\text {th}} </tex-math></inline-formula> dispersion by 60% using the same step voltage and a similar number of pulses. With the proposed scheme, the retention characteristics are also improved by ~43%, and the distribution of <inline-formula> <tex-math notation="LaTeX">\Delta {V}_{\text {th}} </tex-math></inline-formula> is narrowed by ~38%.
A new physics-based model to explain program transient of NAND Flash memory cells is developed in this work. Unlike preexisting model, which incorporated structural features of cylindrical cell ...through an arbitrary adjustment of energy band offset in a planar one, our model is uniquely devised based on cylindrical coordinates, from the beginning. Electrostatic solution from 1-D Poisson equation is used to solve the continuity equation for the free carrier concentration inside charge trap nitride (CTN), and the memory cell is modeled as a capacitor with time-varying charge to track the behavior of its threshold voltage. It is shown that newly proposed model can also predict incremental step pulse programming (ISPP) slope degradation more precisely than the prior model, due to prediction of a larger electric field at the CTN -blocking oxide (BOX) interface, which leads to larger escaping current. The model shows a good fit between the experimental data of three-gate GAA test vehicles and modeling results, displaying a better fit than the previous model.
Flash memory with a charge trap layer (CTL), also known as silicon-oxide-nitride-oxide-silicon (SONOS), is the most common type in production, yet there is a lack of consensus on the physical ...modeling of its operation. In Part I, we therefore proposed a full TCAD model based on an energy relaxation approach and showed that it captures experimentally observed memory operation. This numerical model, however, comes with considerable complexity and computational cost. In Part II, we therefore construct a semianalytical model based on similar physical assumptions, called Pheido, to be as simple as possible. We first derive the model equations based on a balance of current densities, detailing the approximations made. We then use Pheido to analyze the various regimes of an experimental incremental step pulse programming (ISPP) curve and compare it to the full TCAD model derived in Part I. Finally, we investigate the impact of material and structural cell parameters on the ISPP curve, illustrating how the Pheido model offers wide utility at low computational cost.
We present a novel approach to the modeling of carrier energy relaxation during high-field phases in semiconductor-oxide-nitride-oxide-semiconductor (SONOS) flash memory gate stacks. We show that ...this method integrates well with TCAD simulators and that taking the energy relaxation of carriers into consideration solves two of the most prominent problems of trapping layer dynamics modeling: The missing slope degradation in incremental step-pulse programming (ISPP) simulations and the incompatibility of the resulting charge distributions with long-term room temperature charge retention measurements. This article consists of two parts where this part discusses the physical/TCAD level. The second part derives a semianalytical model specifically for programming that reduces the numerical complexity while still retaining the main physical assumptions and the applicability to experimental data.
In this article, we propose a machine learning model-based simulator and method for predicting the threshold voltage (<inline-formula> <tex-math notation="LaTeX">{V}_{\text {t}} ...</tex-math></inline-formula>) distribution of 3-D NAND flash memory. The proposed machine learning modeling method aims to predict each incremental step pulse program (ISPP) slope after ensuring the model's accuracy through training and test using only a small subset of the data from numerous devices that require prediction. As a result of model verification during the test phase of this model after training, the maximum error rate was 2.82%, confirming that high accuracy for prediction was achieved. Using the verified machine learning model, Monte Carlo simulations of random strings are performed, taking into account the factors that influence the formation of the <inline-formula> <tex-math notation="LaTeX">{V}_{\text {t}} </tex-math></inline-formula> distribution. The completed simulator demonstrates the ability to predict <inline-formula> <tex-math notation="LaTeX">{V}_{\text {t}} </tex-math></inline-formula> distribution in various environments, such as quad-level cell (QLC) and penta-level cell (PLC) operations.
The enhancement of program efficiency is essential for fast NAND cell operation. However, it is difficult to simultaneously consider many factors, such as structural parameters and trap ...characteristics, having complex relationships. To overcome these problems, we proposed a neural network (NN)-applied optimization method. First, an optimal network structure was selected by comparing the network performance and learning time. The selected network accurately predicted the threshold voltages of the 21 states of a single NAND cell within a second. Next, an optimization method to improve program efficiency is suggested. The improved NAND cell structure is obtained using a trained NN and numerical method. Here, the optimization required only a few minutes for one optimization process and could consider all parameters simultaneously. Finally, the optimized NAND cell was evaluated using a technology computer-aided design (TCAD) simulation, and its program efficiency was verified. This study shows a specific example of machine learning applied to the semiconductor area, especially in NAND flash memory.
This paper addresses the ongoing challenges to academic freedom in Turkey, site of the 2011 ISPP meeting and a then‐burgeoning cadre of political psychologists working to build the discipline in ...Turkey. In January 2016, the Academics for Peace signed a petition challenging the government's policies towards the Kurds, following which the government began to purge both signatories and other academics. The purge gained traction after the July 2016 attempted coup, which the government put down. Academics and others were dismissed by decree (KHK) and barred from working in any occupation. This paper, a revised version of the 2019 ISPP Presidential Address, discusses the scope of the attack on academic freedom in Turkey and reports on a survey of both dismissed and nondismissed academics in Turkey to discuss the implications of being unexpectedly torn from a position that is as much a calling as it is a job.
