Current hardware implementations of TLS (thread-level speculation) in both Hydra and Renau's SESC simulator use a global component to check data dependence violations, e.g. L2 Cache or hardware list. Frequent memory accesses cause global component bottlenecks. Implementation and verification of the global component dramatically slows the processor's frequency. In this paper, we propose a cache coherence protocol using a distributed data dependence violation checking mechanism for TLS. The proposed protocol extends the current MESI cache coherence protocol by including several methods to exceed the present limits of centralized violation checking methods. In order not to broadcast every exposed write to the snooping bus, the protocol adds an invalidation vector to each private L1 cache to record threads that violate RAW data dependence. It also adds a versioning priority register that compares data versions. Added to each private L1 cache block is a snooping bit which indicates whether the thread possesses a bus snooping right for the block. The L1 Cache gets a bus snooping right when setting snooping bit. The L1 Cache catches exposed read miss whose address matching cache block address field. If a read miss from a remote core with a lower versioning priority, the L1 Cache updates the invalidation vector according to the core ID on the bus. If TLS runtime is going to commit or invalidate a thread, then L1 Cache invalidates threads whose bits have been set in the invalidation vector and changes any cache blocks to a corresponding non-speculative state. In order to implement the proposed protocol, we modified the SESC simulator, which is an open-source cycle-accurate simulator, to confirm its correctness and analyze its performance.