E-resources
-
Schwarzenbach, W.; Allibert, F.; Le Royer, C.; Grenouillet, L.; Malaquin, C.; Bertrand-Giuliani, C.; Boedt, F.; Loubriat, S.; Michau, C.; Parissi, D.; Nguyen, B-Y
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016-Oct.Conference Proceeding
SOI wafers have been used for digital applications for 2 decades. Historically separated between the high-performance, Partially Depleted (PDSOI) 1 and ultra-low power Fully Depleted (FDSOI) 2, the two architectures merged more recently into the UTBB-FDSOI (Ultra-Thin Body & BOX) technology 3. In order to maintain optimum device performance, the buried oxide (BOX) thickness has been scaled from 25nm (28nm node) to 20nm (22nm node). In this paper we present the benefits of further scaling the BOX to 15nm for the next node and describe the process used to fabricate such SOI wafers along with their physical and electrical properties.
Author
![loading ... loading ...](themes/default/img/ajax-loading.gif)
Shelf entry
Permalink
- URL:
Impact factor
Access to the JCR database is permitted only to users from Slovenia. Your current IP address is not on the list of IP addresses with access permission, and authentication with the relevant AAI accout is required.
Year | Impact factor | Edition | Category | Classification | ||||
---|---|---|---|---|---|---|---|---|
JCR | SNIP | JCR | SNIP | JCR | SNIP | JCR | SNIP |
Select the library membership card:
If the library membership card is not in the list,
add a new one.
DRS, in which the journal is indexed
Database name | Field | Year |
---|
Links to authors' personal bibliographies | Links to information on researchers in the SICRIS system |
---|
Source: Personal bibliographies
and: SICRIS
The material is available in full text. If you wish to order the material anyway, click the Continue button.