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Schwarzenbach, W.; Allibert, F.; Le Royer, C.; Grenouillet, L.; Malaquin, C.; Bertrand-Giuliani, C.; Boedt, F.; Loubriat, S.; Michau, C.; Parissi, D.; Nguyen, B-Y
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016-Oct.Conference Proceeding
SOI wafers have been used for digital applications for 2 decades. Historically separated between the high-performance, Partially Depleted (PDSOI) 1 and ultra-low power Fully Depleted (FDSOI) 2, the two architectures merged more recently into the UTBB-FDSOI (Ultra-Thin Body & BOX) technology 3. In order to maintain optimum device performance, the buried oxide (BOX) thickness has been scaled from 25nm (28nm node) to 20nm (22nm node). In this paper we present the benefits of further scaling the BOX to 15nm for the next node and describe the process used to fabricate such SOI wafers along with their physical and electrical properties.
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