E-resources
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Liu, Q.; DeSalvo, B.; Morin, P.; Loubet, N.; Pilorget, S.; Chafik, F.; Maitrejean, S.; Augendre, E.; Chanemougame, D.; Guillaumet, S.; Kothari, H.; Allibert, F.; Lherron, B.; Liu, B.; Escarabajal, Y.; Cheng, K.; Kuss, J.; Wang, M.; Jung, R.; Teehan, S.; Levin, T.; Sankarapandian, M.; Johnson, R.; Kanyandekwe, J.; He, H.; Venigalla, R.; Yamashita, T.; Haran, B.; Grenouillet, L.; Vinet, M.; Weber, O.; Josse, E.; Boeuf, F.; Haond, M.; Bataillon, J.-L; Kleemeier, W.; Skotnicki, T.; Khare, M.; Faynot, O.; Doris, B.; Celik, M.; Sampson, R.
2014 IEEE International Electron Devices Meeting, 2014-Dec.Conference Proceeding
We report FDSOI devices with a 20nm gate length (L G ) and 5nm spacer, featuring a 20% tensile strained Silicon-on-Insulator (sSOI) channel NFET and 35% Ge partially compressive strained SiGe-on-Insulator (SGOI) channel PFET. This work represents the first demonstration of strain reversal of sSOI by SiGe in short channel devices. At V dd of 0.75V, competitive effective current (I eff ) reaches 550/340 μA/μm for NFET, at I off of 100/1 nA/μm, respectively. With a fully strained 30% SGOI channel on thin BOX (20nm) substrate and V dd of 0.75V, PFET I eff reaches 495/260 μA/μm, at I off of 100/1 nA/μm, respectively. Competitive sub-threshold slope and DIBL are reported. With the demonstrated advanced strain techniques and short channel performance, FDSOI devices can be extended for both high performance and low power applications to the 10nm node.
